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参数资料
| 型号： | ICS1562BM-201T |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO CLK SYNTHESIZER 16-SOIC |
| 产品变化通告： | Product Discontinuation 13/May/2009 |
| 标准包装： | 2,500 |
| 类型： | 时钟/频率合成器，时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，TTL，晶体 |
| 输出： | CMOS，PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 260MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
| 其它名称： | 1562BM-201T |
Pin Descriptions - ICS1562B-001
PIN#
NAME
DESCRIPTION
10
CLK+
Clock out (non-inverted)
9CLK
Clock out (inverted)
7
LOAD
Load output. This output is normally at the CLK frequency divided by N1.
2
XTAL1
Quartz crystal connection 1/external reference frequency input
3
XTAL2
Quartz crystal connection 2
1
AD0
Address/Data Bit 0 (LSB)
16
AD1
Address/Data Bit 1
15
AD2
Address/Data Bit 2
14
AD3
Address/Data Bit 3 (MSB)
8
LD/N2
Divided LOAD output. See text.
4
STROBE
Control for address/data latch
13
VDD
PLL system power (+5V. See application diagram.)
12
VDDO
Output stage power (+5V)
11
IPRG
Output stage current set
5,6
VSS
Device ground. Both pins must be connected to the same ground potential.
Pin Descriptions - ICS1562B-201
PIN#
NAME
DESCRIPTION
10
CLK+
Clock out (non-inverted)
9CLK
Clock out (inverted)
7
LOAD
Load output. This output is normally at the CLK frequency divided by N1.
2
XTAL1
Quartz crystal connection 1/external reference frequency input
3
XTAL2
Quartz crystal connection 2
4
DATCLK
Data Clock (Input)
16
DATA
Serial Register Data (Input)
15
HOLD~
HOLD (Input)
14
BLANK
Blanking (Input). See Text.
8
LD/N2
Divided LOAD output/shift clock. See text.
1
EXTFBK
External feedback connection for PLL (input). See text.
13
VDD
PLL system power (+5V. See application diagram.)
12
VDDO
Output stage power (+5V)
11
IPRG
Output stage current set
5,6
VSS
Device ground. Both pins must be connected.
ICS1562B
15
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| ICS1562BM-XXX | 制造商:ICS 制造商全称:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
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