- 您现在的位置：买卖IC网 > PDF目录65534 > ICS9112M-18T (INTEGRATED DEVICE TECHNOLOGY INC) 91 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 PDF资料下载
参数资料
| 型号： | ICS9112M-18T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 91 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 2/4页 |
| 文件大小： | 52K |
| 代理商： | ICS9112M-18T |
ICS9112-18
Zero Delay, Low Skew Buffer
ADVANCE INFORMATION
MDS9112-18B
2
Revision 12038
Printed 12/11/98
Integrated Circuit Systems 525 Race Street San Jose CA 95126 (408)295-9800tel(408)295-9818fax
Pin Descriptions
Key: I = Input; O = output; P = power supply connection.
Pin Assignment
ICS9112-18
External Components
The ICS9112-18 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1F should be connected between VDD and GND on pins 4 and 5, and VDD and GND
on pins 13 and 12, as close to the device as possible. A series termination resistor of 33
may be used close
to the pin for each clock output to reduce reflections.
16
15
14
13
16 pin narrow (150 mil) SOIC
12
11
10
9
1
2
3
4
5
6
7
8
CLKA1
GND
FBIN
CLKIN
VDD
S2
CLKB1
CLKB2
VDD
GND
CLKB3
S1
CLKB4
CLKA4
CLKA3
CLKA2
S2
S1
Clocks A1-A4
Clocks B1-B4
Internal Generation
PLL Status
0
Tri-state (high impedance)
None
On
0
1
Running
Tri-state (high impedance)
PLL
On
1
0
Running
Buffer Only (no zero delay)
Off
1
Running
PLL
On
Feedback From
CLKA1:A4
CLKB1:B4
Bank A
CLKIN
CLKIN/2
Bank B
2XCLKIN
CLKIN
Number
Name
Type
Description
1
CLKIN
I
CLocK INput. Connect to input clock source.
2, 3, 14, 15
CLKA1:4
O
CLocK A bank of four outputs.
4, 13
VDD
P
Power supply. Connect both pins to same voltage (either 3.3V or 5V).
5, 12
GND
P
Connect to ground.
6, 7, 10, 11
CLKB1:4
O
CLocK B bank of four outputs. These are low skew divide by two of bank A.
8
S2
I
Select input #2. Selects mode for outputs per table above.
9
S1
I
Select input #1. Selects mode for outputs per table above.
16
FBIN
I
FeedBack INput. Determines outputs per Feedback Configuration Table above.
Output Clock Mode Select Table
Feedback Configuration Table
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9112YG-16-T | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112YG-27LF-T | LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112YG-27LF-T | LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112YM-17-T | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS9112YM-17-T | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9112M-22 | 功能描述:IC CLK BUFFER DVR 133MHZ 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS9112M-31 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
| ICS9112M-32 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
| ICS9112M-33 | 功能描述:IC CLOCK DRIVER LO JITTER 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS9112M-33T | 功能描述:IC CLOCK DRIVER LO JITTER 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。