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| 型号： | ICS9112M-18T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 91 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 3/4页 |
| 文件大小： | 52K |
| 代理商： | ICS9112M-18T |
ICS9112-18
Zero Delay, Low Skew Buffer
ADVANCE INFORMATION
MDS9112-18B
3
Revision 12038
Printed 12/11/98
Integrated Circuit Systems 525 Race Street San Jose CA 95126 (408)295-9800tel(408)295-9818fax
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
-0.5
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Electrostatic Discharge
MIL-STD-883
2000
V
Ambient Operating Temperature
0
70
C
Soldering Temperature
Max of 10 seconds
260
C
Junction temperature
150
C
Storage temperature
-65
150
C
DC CHARACTERISTICS
Operating Voltage, VDD
3.00
5.50
V
Input High Voltage, VIH, CLKIN pin only
VDD/2+1
VDD/2
V
Input Low Voltage, VIL, CLKIN pin only
VDD/2
VDD/2-1
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load
TBD
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance
S2, S1, FBIN
7
pF
AC CHARACTERISTICS
Input Clock Frequency
TBD
135
MHz
Output Clock Frequency
TBD
135
MHz
Output Clock Rise Time, CL=30pF
0.8 to 2.0V
1.5
ns
Output Clock Fall Time, CL=30pF
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle, VDD=3.3V
At 1.4V
40
50
60
%
Device to Device Skew, equally loaded
rising edges at VDD/2
700
ps
Output to Output Skew, equally loaded
rising edges at VDD/2
250
ps
Maximum Absolute Jitter
TBD
ps
Cycle to Cycle Jitter, 30pF loads
66.67 MHz outputs
500
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
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