- 您现在的位置：买卖IC网 > PDF目录67705 > ICS9148YF-12 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 PDF资料下载
参数资料
| 型号： | ICS9148YF-12 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 14/18页 |
| 文件大小： | 476K |
| 代理商： | ICS9148YF-12 |
5
ICS9148-12
MODE
This Input pin is used to select the Input function of the
I/O pins. An active Low will place the I/O pins in the
Input mode and enable those stop clock functions.
CPU3.3_2.5#
This Input pin controls the CPU and IOAPIC output
buffer strength for skew matching CPU and SDRAM
outputs to compensate for the external VDDL supply
condition. It is important to use this function when
selecting power supply requirements for VDDL1,2. A
logic “0” (ground) will indicate 2.5V operation and a
logic “1” will indicate 3.3V operation. This pin has an
internal pullup resistor to VDD.
PWR_DWN#
This is an asynchronous active Low Input pin used to
Power Down the device into a Low Power state by not
removing the power supply. The internal Clocks are
disabled and the VCO and Crystal are stopped. Powered
Down will also place all the Outputs in a low state at the
end of their current cycle. The latency of Power Down
will not be greater than 3ms. The I
2C inputs will be Tri-
Stated and the device will retain all programming
information. This input pin only valid when MODE=0
(Power Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop
the CPUCLK clocks in an active low state. All other
Clocks including SDRAM clocks will continue to run
while this function is enabled. The CPUCLK’s will have
a turn ON latency of at least 3 CPU clocks. This input
pin only valid when MODE=0 (Power Management
Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop
the PCICLK clocks in an active low state. It will not
effect PCICLK_F nor any other outputs. This input pin
only valid when MODE=0 (Power Management Mode)
I
2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device
in the I
2C protocol. It will allow read-back of the
registers. See configuration map for register functions.
The I
2C specification in Philips I2C Peripherals Data
Handbook (1996) should be followed.
Technical Pin Function Descriptions
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9148YF-12LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148YF-37LF-T | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148YF-82LF | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS91718YGLF-T | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS91730YMLF-T | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9148YF-17-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148YF-36 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148YF-46 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148YF-60 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148YF-82 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
发布紧急采购，3分钟左右您将得到回复。