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参数资料
| 型号： | ICS9148YF-12 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 2/18页 |
| 文件大小： | 476K |
| 代理商： | ICS9148YF-12 |
10
ICS9148-12
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-12. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9148-12 internally. The minimum that the PCICLK (0:5) clocks
are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low
state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising
PCICLK clock off latency is one PCICLK clock.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power
operation.CPU_STOP# is synchronized by the ICS9148-12.The minimum that the CPUCLK is enabled (CPU_STOP#
high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
(Drawing shown on next
page.)
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may
exist. This signal is synchronized to the CPUCLKs inside the ICS9148-
12.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
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相关代理商/技术参数 |
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| ICS9148YF-17-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
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| ICS9148YF-46 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148YF-60 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148YF-82 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
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