- 您现在的位置：买卖IC网 > PDF目录67707 > ICS94252YFLF-T (INTEGRATED DEVICE TECHNOLOGY INC) 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 PDF资料下载
参数资料
| 型号： | ICS94252YFLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, LEAD FREE, MO-118, SSOP-48 |
| 文件页数： | 17/19页 |
| 文件大小： | 136K |
| 代理商： | ICS94252YFLF-T |
7
ICS94252
0456B—04/12/04
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B3
41
0
M
A
R
D
S
6
t
i
B2
41
1
M
A
R
D
S
5
t
i
B9
31
2
M
A
R
D
S
4
t
i
B8
31
3
M
A
R
D
S
3
t
i
B7
31
4
M
A
R
D
S
2
t
i
B6
31
5
M
A
R
D
S
1
t
i
B3
31
6
M
A
R
D
S
0
t
i
B2
31
7
M
A
R
D
S
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
X
#
0
S
F
6
t
i
B-
X
#
1
S
F
5
t
i
B-
X
#
2
S
F
4
t
i
B1
31
8
M
A
R
D
S
3
t
i
B0
31
9
M
A
R
D
S
2
t
i
B7
21
0
1
M
A
R
D
S
1
t
i
B6
21
1
M
A
R
D
S
0
t
i
B5
21
2
1
M
A
R
D
S
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
X
#
3
S
F
6
t
i
B0
11
1
P
G
A
5
t
i
B9
1
0
P
G
A
4
t
i
B2
21
z
H
M
8
4
3
t
i
B2
1
C
I
P
A
O
I
2
t
i
B7
1
X
2
r
o
X
1
-
0
F
E
R
X
1
=
1
=
t
l
u
a
f
e
d
1
t
i
B6
41
1
K
L
C
U
P
C
0
t
i
B7
41
0
K
L
C
U
P
C
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
X
#
E
D
O
M
6
t
i
B0
21
5
K
L
C
I
C
P
5
t
i
B9
11
4
K
L
C
I
C
P
4
t
i
B8
11
3
K
L
C
I
C
P
3
t
i
B5
11
2
K
L
C
I
C
P
2
t
i
B4
11
1
K
L
C
I
C
P
1
t
i
B3
11
0
K
L
C
I
C
P
0
t
i
B2
11
F
_
K
L
C
I
C
P
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B5
11
#
T
E
S
E
R
=
0
,
2
K
L
C
I
C
P
=
1
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B-
0
l
i
w
P
O
T
S
_
U
P
C
0
=
)
0
:
1
(
t
i
B
s
k
c
o
l
c
U
P
C
p
o
t
s
l
i
w
P
O
T
S
_
U
P
C
1
0
=
)
0
:
1
(
t
i
B
s
k
c
o
l
c
P
G
A
,
M
A
R
D
S
,
U
P
C
p
o
t
s
l
i
w
P
O
T
S
_
U
P
C
0
1
=
)
0
:
1
(
t
i
B
s
k
c
o
l
c
M
A
R
D
S
,
U
P
C
p
o
t
s
l
i
w
P
O
T
S
_
U
P
C
1
=
)
0
:
1
(
t
i
B
s
k
c
o
l
c
P
G
A
,
U
P
C
p
o
t
s
0
t
i
B-
0
相关PDF资料 |
PDF描述 |
|---|---|
| ICS950104YFT | 166 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS950201YFT | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS950201YFT | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS950201YF-T | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS950201YGLF-T | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS948AI147L | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER |
| ICS950104 | 制造商:ICS 制造商全称:ICS 功能描述:Programmable System Clock Chip for PIII Processor |
| ICS950104YFT | 制造商:ICS 制造商全称:ICS 功能描述:Programmable System Clock Chip for PIII Processor |
| ICS950201 | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub⑩ for P4⑩ |
| ICS950201AFLF | 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
发布紧急采购，3分钟左右您将得到回复。