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参数资料
| 型号： | ICS94252YFLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, LEAD FREE, MO-118, SSOP-48 |
| 文件页数： | 8/19页 |
| 文件大小： | 136K |
| 代理商： | ICS94252YFLF-T |
16
ICS94252
0456B—04/12/04
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94252. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94252 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94252 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94252.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCICLK
PCI_STOP#
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