参数资料
型号: ICS952623YGLFT
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
文件页数: 14/27页
文件大小: 321K
代理商: ICS952623YGLFT
21
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
CPU_Stop = Driven, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")
CPU Clock Tristate Timing
CPU_Stop = Tristate, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.
相关PDF资料
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ICS952624YFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS952702YFLFT 222 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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ICS954101YGLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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