参数资料
型号: ICS952623YGLFT
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
文件页数: 15/27页
文件大小: 321K
代理商: ICS952623YGLFT
22
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
CPU_Stop = Driven, CPU_Pwrdwn = Tristate
CPU_Stop#
1.8mS
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the
assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected.
2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately
after the 1.8mS windows expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
CPU_Stop = Tristate, CPU_Pwrdwn = Tristate
CPU_Stop#
1.8mS
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of
CPU_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
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