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参数资料
| 型号： | ICS952623YGLFT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56 |
| 文件页数： | 16/27页 |
| 文件大小： | 321K |
| 代理商： | ICS952623YGLFT |
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23
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and
SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
SRC_Stop = Driven, SRC_Pwrdwn = Driven
PCI_Stop#
1.8mS
PWRDWN#
PCI (Free Running)
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output
clock (assuming clock's OE bit is set to "1")
SRC Clock Tristate Timing
SRC_Stop = Tristate, Pwrdwn = Tristate
PCI_Stop#
1.8mS
PWRDWN#
PCI (Free Running)
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of
PCI_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS952623YGT | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952702 | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for K7 System |
| ICS952702YFLF-T | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for K7 System |
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| ICS952703BF | 功能描述:IC TIMING CTRL HUB K7 48-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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