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参数资料
型号： ICS952623YGLFT
元件分类： 时钟产生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
文件页数： 21/27页
文件大小： 321K
代理商： ICS952623YGLFT
3
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
Pin Description (Continued)
PIN
#
PIN NAME
PIN TYPE
DESCRIPTION
29
3V66_4/VCH
OUT
66.66MHz clock output for AGP support. AGP-PCI should be
aligned with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
30
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
31
48MHz_USB
OUT
48MHz clock output.
32
48MHz_DOT
OUT
48MHz clock output.
33
GND
PWR
Ground pin.
34
VDD48
PWR
Power for 48MHz output buffers and fixed PLL core.
35
Vtt_PWRGD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
36
VDD
PWR
Power supply for SRC clocks, nominal 3.3V
37
SRCCLKC
OUT
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
38
SRCCLKT
OUT
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
39
GND
PWR
Ground pin.
40
CPUCLKC0
OUT
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
41
CPUCLKT0
OUT
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
42
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
43
CPUCLKC1
OUT
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
44
CPUCLKT1
OUT
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
45
GND
PWR
Ground pin.
46
CPUCLKC2
OUT
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
47
CPUCLKT2
OUT
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
48
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
49
PCI_STOP#
IN
Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at
logic 0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.
50
CPU_STOP#
IN
Stops all CPUCLK besides the free running clocks. Internal pull-up
of 150K nominal
51
FS_A
IN
Frequency select pin, see Frequency table for functionality
52
IREF
OUT
IREF establishes the reference current for the CPUCLK pairs. A
fixed precision resistor tied to ground is required to establish the
appropriate current.
53
GND
PWR
Ground pin.
54
GNDA
PWR
Ground pin for core.
55
VDDA
PWR
3.3V power for the PLL core.
56
FS_B
IN
Frequency select pin, see Frequency table for functionality
相关PDF资料
PDF描述
ICS952624YFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS952702YFLFT 222 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS952702YFT 222 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS952703YFLFT 217.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS954101YGLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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