参数资料
型号: IDT7007L20G
厂商: IDT, Integrated Device Technology Inc
文件页数: 16/21页
文件大小: 0K
描述: IC SRAM 256KBIT 20NS 68PGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 256K (32K x 8)
速度: 20ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-BPGA
供应商设备封装: 68-PGA(29.46x29.46)
包装: 托盘
其它名称: 7007L20G
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Waveform of Interrupt Timing (1)
t WC
Military, Industrial and Commercial Temperature Ranges
ADDR "A"
INTERRUPT SET ADDRESS
(2)
t AS (3)
t WR
(4)
CE "A"
R/ W "A"
t INS (3)
INT "B"
2940 drw 17
t RC
ADDR "B"
INTERRUPT CLEAR ADDRESS
(2)
t AS (3)
CE "B"
OE "B"
t INR (3)
INT "B"
2940 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/ W ) is de-asserted first.
Truth Table III — Interrupt Flag (1)
Left Port
Right Port
L
H
L
H
R/ W L
L
X
X
X
CE L
L
X
X
L
OE L
X
X
X
L
A 14L -A 0L
7FFF
X
X
7FFE
INT L
X
X
(3)
(2)
R/ W R
X
X
L
X
CE R
X
L
L
X
OE R
X
L
X
X
A 14R -A 0R
X
7FFF
7FFE
X
INT R
(2)
(3)
X
X
Function
Set Right INT R Flag
Reset Right INT R Flag
Set Left INT L Flag
Reset Left INT L Flag
2940 tbl 16
NOTES:
1. Assumes BUSY L = BUSY R =V IH .
2. If BUSY L = V IL , then no change.
3. If BUSY R = V IL , then no change.
16
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