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| 型号： | IDT7007L20G |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 17/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 256KBIT 20NS 68PGA |
| 标准包装： | 3 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 256K (32K x 8) |
| 速度： | 20ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-BPGA |
| 供应商设备封装： | 68-PGA（29.46x29.46） |
| 包装： | 托盘 |
| 其它名称： | 7007L20G |
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Truth Table IV — Address BUSY
Arbitration
Military, Industrial and Commercial Temperature Ranges
Inputs
Outputs
CE L
X
H
X
L
CE R
X
X
H
L
A OL -A 14L
A OR -A 14R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
(2)
BUSY R (1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit (3)
2940 tbl 17
NOTES:
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7007 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY R outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
NOTES:
D 0 - D 7 Left
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 7 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2940 tbl 18
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007.
2. There are eight semaphore flags written to via I/O 5 (I/O 0 - I/O 7 ) and read from all I/O 0 . These eight semaphores are addressed by A 0 - A 2 .
3. CE = V IH , SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7007 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7007 has an automatic power down feature controlled
by CE . The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected ( CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
INTERRUPTS
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
( INT L ) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CE = R/ W = V IL per the Truth Table.
The left port clears the interrupt through access of address location 7FFE
17
when CE R = OE R = V IL , R/ W is a "don't care". Likewise, the right port
interrupt flag ( INT R ) is asserted when the left port writes to memory location
7FFF (HEX) and to clear the interrupt flag ( INT R ), the right port must read
the memory location 7FFF. The message (8 bits) at 7FFE or 7FFF is user-
defined since it is an addressable SRAM location. If the interrupt function
is not used, address locations 7FFE and 7FFF are not used as mail boxes,
but as part of the random access memory. Refer to Table III for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of
the two accesses to proceed and signals the other side that the RAM is
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相关代理商/技术参数 |
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|---|---|
| IDT7007L20GB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L20GI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L20J | 功能描述:IC SRAM 256KBIT 20NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT7007L20J8 | 功能描述:IC SRAM 256KBIT 20NS 68PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT7007L20JB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
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