参数资料
型号: IDT7009L20PFI
厂商: IDT, Integrated Device Technology Inc
文件页数: 5/17页
文件大小: 0K
描述: IC SRAM 1MBIT 20NS 100TQFP
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 1M (128K x 8)
速度: 20ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 7009L20PFI
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (2) (V CC = 5.0V ± 10%)
7009L
Input Leakage Current
Symbol
|I LI |
|I LO |
V OL
V OH
Parameter
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V CC = 5.5V, V IN = 0V to V CC
CE = V IH , V OUT = 0V to V CC
I OL = 4mA
I OH = -4mA
Min.
___
___
___
2.4
Max.
5
5
0.4
___
Unit
μA
μA
V
V
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1) (V CC = 5.0V ± 10%)
7009L15
Com'l Only
7009L20
Com'l & Ind
4839 tbl 09
Symbol
Parameter
Test Condition
Version
Typ. (1) Max
Typ. (1) Max
Unit
I CC
I SB1
I SB2
I SB3
I SB4
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level
Inputs)
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE = V IL , Outputs Disabled
SEM = V IH
f = f MAX (2)
CE L = CE R = V IH
SEM R = SEM L = V IH
f = f MAX (2)
CE "A" = V IL and CE "B" = V IH (4)
Active Port Outputs Disabled,
f=f MAX (2) , SEM R = SEM L = V IH
Both Ports CE L and
CE R > V CC - 0.2V, V IN > V CC - 0.2V
or V IN < 0.2V, f = 0 (3)
SEM R = SEM L > V CC - 0.2V
CE "A" < 0.2V and
CE "B" > V CC - 0.2V (4) ,
SEM R = SEM L > V CC - 0.2V,
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
L
L
L
L
L
L
L
L
L
220
____
65
____
145
____
0.2
____
135
340
____
100
____
225
____
3.0
____
220
200
200
50
50
130
130
0.2
0.2
120
300
360
75
120
195
235
3.0
6.0
190
mA
mA
mA
mA
mA
V IN > V CC - 0.2V or V IN < 0.2V,
Active Port Outp uts Disabled , f = f MAX (2)
IND
L
____
____
120
230
NOTES:
4839 tbl 10
1. V CC = 5V, T A = +25°C, and are not production tested. I CCDC = 120mA (Typ.)
2. At f = f MAX , address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ t RC, and using “AC Test Conditions” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Chip Enable Truth Table.
5
6.42
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