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| 型号： | IDT70P258L55BYI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 55NS 100BGA |
| 标准包装： | 90 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K（8K x 16） |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-VFBGA |
| 供应商设备封装： | 100-CABGA（6x6） |
| 包装： | 托盘 |
| 其它名称： | 70P258L55BYI |
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,5,8)
t WC
ADDRESS
t HZ (7)
OE
CE or SEM
CE or SEM
(9)
(9)
t AW
R/ W
DATA OUT
t AS (6)
(4)
t WZ (7)
t WP (2)
t DW
t WR (3)
t OW
t DH
(4)
DATA IN
,
5675 drw 06
Timing Waveform of Write Cycle No. 2, CE , UB , LB Controlled Timing (1,5)
t WC
ADDRESS
CE or SEM
(9)
t AW
UB or LB
(9)
t AS (6)
t EW (2)
t WR (3)
R/ W
DATA IN
t DW
t DH
5675 drw 07
,,
NOTES:
1. R/ W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a low UB or LB and a LOW CE and a LOW R/ W for memory array writing cycle.
3. t WR is measured from the earlier of CE or R/ W going HIGH (or SEM going LOW) to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE , R/ W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output
Test Load.
8. If OE is LOW during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off and data to be placed on the
bus for the required t DW . If OE is HIGH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .
9. To access SRAM, CE = V IL , UB or LB = V IL , SEM = V IH . To access semaphore, CE = V IH or UB and LB = V IH and SEM = V IL . Either condition must be valid for
the entire t EW time.
11
6.42
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相关代理商/技术参数 |
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|---|---|
| IDT70P258L55BYI8 | 功能描述:IC SRAM 128KBIT 55NS 100BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT70P259L65BYGI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 65NS 100FPBGA |
| IDT70P259L65BYGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 65NS 100FPBGA |
| IDT70P259L90BYGI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 90NS 100FPBGA |
| IDT70P259L90BYGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 90NS 100FPBGA |
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