参数资料
型号: IDT70P258L55BYI
厂商: IDT, Integrated Device Technology Inc
文件页数: 3/23页
文件大小: 0K
描述: IC SRAM 128KBIT 55NS 100BGA
标准包装: 90
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 128K(8K x 16)
速度: 55ns
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: -40°C ~ 85°C
封装/外壳: 100-VFBGA
供应商设备封装: 100-CABGA(6x6)
包装: 托盘
其它名称: 70P258L55BYI
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Pin Names
Industrial Temperature Range
CE L
R/ W L
OE L
Left Port
Right Port
CE R
R/ W R
OE R
Names
Chip Enable (Input)
Read/Write Enable (Input)
Output Enable (Input)
A 0R - A 12R
A 0L - A 12L
(1)
(1)
Address (Input)
I/O 0L - I/O 15L
SEM L
UB L
LB L
INT L
BUSY L
I/O 0R - I/O 15R
SEM R
UB R
LB R
INT R
BUSY R
Data Input/Output
Semaphore Enable (Input)
Upper Byte Select (Input)
Lower Byte Select (Input)
Interrupt Flag (Output)
Busy Flag
IRR 0 , IRR 1
ODR 0 - ODR 4
SFEN (2)
M/ S
V DD
V DDQL
V SS
Input Read Register (Input)
Output Drive Register (Output)
Special Function Enable (Input)
Master or Slave Select (Input)
Power (1.8V) (Input)
Left Port I/O Supply Voltage
(2.5V or 3.0V) (Input)
Ground (0V) (Input)
NOTE:
1. A 12X is a NC for IDT70P248.
2. SFEN is active when either CE L = V IL or CE R = V IL .
SFEN is inactive when CE L = CE R = V IH .
5675 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs (1)
Outputs
CE
H
X
L
L
L
L
L
L
X
R/ W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O 8-15
High-Z
High-Z
DATA IN
High-Z
DATA IN
DATA OUT
High-Z
DATA OUT
High-Z
I/O 0-7
High-Z
High-Z
High-Z
DATA IN
DATA IN
High-Z
DATA OUT
DATA OUT
High-Z
Mode
Deselected: Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
NOTE:
1. A 0L — A 12L ≠ A 0R — A 12R
3
6.42
5675 tbl 02
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