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| 型号： | IDT70P258L55BYI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 21/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 55NS 100BGA |
| 标准包装： | 90 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K（8K x 16） |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-VFBGA |
| 供应商设备封装： | 100-CABGA（6x6） |
| 包装： | 托盘 |
| 其它名称： | 70P258L55BYI |
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Output Drive Register
The Output Drive Register (ODR) of the IDT70P258/248 determines
the state of up to five external binary-state devices by providing a path to
V SS for the external circuit. The five external devices supported by the ODR
can operate at different voltages (1.5V < V SUPPLY < 3.5V), but the combined
current of the devices must not exceed 40 mA (8mA I MAX for each external
device). The status of the ODR bits is set using standard write accesses
from either port to address x0001with a “1” corresponding to “on“ and a
“0” corresponding to “off”. The status of the ODR bits can also be read
(without changing the status of the bits) via a standard read to address
x0001. When SFEN = V IL , the ODR is active and address x0001 is not
available for standard memory operations. When SFEN = V IH , the ODR
is inactive and address x0001 can be used as part of the main memory.
During reads and writes to the ODR I/O 0 - I/O 4 are valid bits and I/O 5 -
I/O 15 are "Don't Care". Refer to Figure 4 and Truth Table VII for Output
Drive Register operation.
Semaphores
The IDT70P258/248 is an extremely fast Dual-Port 8K/4K x 16 CMOS
Static RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right side
of the Dual-Port SRAM to claim a privilege over the other processor for
functions defined by the system designer’s software. As an example, the
semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port SRAM or any other shared resource.
The Dual-Port SRAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be accessed
to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
have an automatic power-down feature controlled by CE , the Dual-Port
SRAM enable, and SEM , the semaphore enable. The CE and SEM pins
control on-chip power down circuitry that permits the respective port to go
into standby mode when not selected. This is the condition which is shown
in Truth Table I where CE and SEM are LOW.
Systems which can best use the IDT70P258/248 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems can
benefit from a performance increase offered by the IDT70P258/248's
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70P258/248 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
Industrial Temperature Range
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port SRAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active HIGH. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT70P258/248 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts as
a chip select for the semaphore flags) and using the other control pins
(Address, OE , and R/ W ) as they would be used in accessing a standard
Static RAM. Each of the flags has a unique address which can be accessed
by either side through address pins A 0 – A 2 . When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D 0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select ( SEM ) and output enable ( OE )
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal ( SEM or OE ) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
21
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT70P258L55BYI8 | 功能描述:IC SRAM 128KBIT 55NS 100BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT70P259L65BYGI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 65NS 100FPBGA |
| IDT70P259L65BYGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 65NS 100FPBGA |
| IDT70P259L90BYGI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 90NS 100FPBGA |
| IDT70P259L90BYGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 128KBIT 90NS 100FPBGA |
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