- 您现在的位置：买卖IC网 > Datasheet目录329 > IDT70V08S15PF (IDT, Integrated Device Technology Inc)IC SRAM 512KBIT 15NS 100TQFP Datasheet资料下载
参数资料
| 型号： | IDT70V08S15PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 512KBIT 15NS 100TQFP |
| 标准包装： | 45 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 512K (64K x 8) |
| 速度： | 15ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 70V08S15PF |
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
address locations FFFE and FFFF are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table IV for the
interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “Busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY logic is not desirable, the BUSY logic can be disabled by placing
the part in slave mode with the M/ S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
A 16
Industrial and Commercial Temperature Ranges
of the array and another master indicating BUSY on one other side of the
array. This would inhibit the write operations from one port for part of a word
and inhibit the write operations from the other port for the other part of the
word.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/ W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Semaphores
The IDT70V08 is an extremely fast Dual-Port 64K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an ex-
ample, the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port RAM or any other
shared resource.
The Dual-Port RAM features a fast access time, with both ports
being completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right port.
MASTER
Dual Port RAM
CE 0
SLAVE
Dual Port RAM
CE 0
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
BUSY L
BUSY R
BUSY L
BUSY R
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
Dual Port RAM
BUSY L BUSY R
MASTER CE 1
Dual Port RAM
BUSY L BUSY R
SLAVE CE 1
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE , the Dual-Port RAM enable, and SEM , the
semaphore enable. The CE and SEM pins control on-chip power
3740 drw 17
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V08 RAMs.
that port LOW.
The BUSY outputs on the IDT 70V08 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V08 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70V08 RAM the BUSY pin is an output if the part is used as a
master (M/ S pin = V IH ), and the BUSY pin is an input if the part used
as a slave (M/ S pin = V IL ) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
18
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
III where CE and SEM are both HIGH.
Systems which can best use the IDT70V08 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V08s
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V08 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
相关PDF资料 |
PDF描述 |
|---|---|
| IDT70V09L20PFI | IC SRAM 1MBIT 20NS 100TQFP |
| IDT70V18L20PFI | IC SRAM 576KBIT 20NS 100TQFP |
| IDT70V25L55G | IC SRAM 128KBIT 55NS 84PGA |
| IDT70V261L25PFGI | IC SRAM 256KBIT 25NS 100TQFP |
| IDT70V26L35G | IC SRAM 256KBIT 35NS 84PGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT70V08S15PF8 | 功能描述:IC SRAM 512KBIT 15NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V08S20PF | 功能描述:IC SRAM 512KBIT 20NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V08S20PF8 | 功能描述:IC SRAM 512KBIT 20NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V08S25PF | 功能描述:IC SRAM 512KBIT 25NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V08S25PF8 | 功能描述:IC SRAM 512KBIT 25NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
发布紧急采购，3分钟左右您将得到回复。