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| 型号： | IDT70V261L25PFGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 256KBIT 25NS 100TQFP |
| 标准包装： | 45 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 256K（16K x 16） |
| 速度： | 25ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 70V261L25PFGI |
IDT70V261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Functional Description
The IDT70V261 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V261 has an automatic power down
feature controlled by CE . The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not selected
( CE HIGH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag ( INT L ) is asserted when the right port writes to memory location
3FFE (HEX), where a write is defined as CE R = R/ W R = V IL per Truth
Table III. The left port clears the interrupt through access of address
location 3FFE when CE L = OE L = V IL , R/ W is a "don't care". Likewise,
the right port interrupt flag ( INT R ) is asserted when the left port writes
to memory location 3FFF (HEX) and to clear the interrupt flag ( INT R ),
the right port must read the memory location 3FFF. The message (8
bits) at 3FFE or 3FFF is user-defined since it is an addressable SRAM
location. If the interrupt function is not used, address locations 3FFE
and 3FFF are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table III for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the write
signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any busy indication as an interrupt source to flag an
illegal or illogical operation. If the write inhibit function of BUSY logic
is not desirable, the BUSY logic can be disabled by placing the part in
slave mode with the M/ S pin. Once in slave mode the BUSY pin
operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
Industrial and Commercial Temperature Ranges
write operations can be prevented to a port by tying the BUSY pin for that
port LOW.
The BUSY outputs on the IDT70V261 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V261 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70V261 SRAM the BUSY pin is an output if the part is used as a
master (M/ S pin = V IH ), and the BUSY pin is an input if the part used
as a slave (M/ S pin = V IL ) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for part of
the other word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/ W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
Semaphores
The IDT70V261 is a fast Dual-Port 16K x 16 CMOS Static RAM with
an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-
Port SRAM to claim a privilege over the other processor for functions
defined by the system designer’s software. As an example, the
semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port SRAM or any other shared
resource.
The Dual-Port SRAM features a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
MASTER
Dual Port
RAM
BUSY L
CE
BUSY R
SLAVE
Dual Port
RAM
BUSY L
CE
BUSY R
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
BUSY L
MASTER
Dual Port
RAM
BUSY L
CE
BUSY R
SLAVE
Dual Port
RAM
BUSY L
CE
BUSY R
BUSY R
3040 drw 17
,
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE , the Dual-Port SRAM enable, and SEM , the
semaphore enable. The CE and SEM pins control on-chip power down
circuitry that permits the respective port to go into standby mode when
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V261 RAMs.
not selected. This is the condition which is shown in Truth Table I where
CE and SEM are both HIGH.
14
6.42
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| IDT70V261L25PFGI8 | 功能描述:IC SRAM 256KBIT 25NS 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V261L25PFI | 功能描述:IC SRAM 256KBIT 25NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,500 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（单线） 电源电压:1.8 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-MSOP 包装:带卷 (TR) |
| IDT70V261L25PFI8 | 功能描述:IC SRAM 256KBIT 25NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V261L35PF | 功能描述:IC SRAM 256KBIT 35NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V261L35PF8 | 功能描述:IC SRAM 256KBIT 35NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
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