参数资料
型号: IDT70V3579S5DRI
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/17页
文件大小: 0K
描述: IC SRAM 1.125MBIT 5NS 208QFP
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 1.125M(32K x 36)
速度: 5ns
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: -40°C ~ 85°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
包装: 托盘
其它名称: 70V3579S5DRI
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) (2)
t CYC2
CLK
CE 0
t CH2
t CL2
CE 1
t SC
t SB
t HC
t HB
BE n
t SW t HW
R/ W
t SW t HW
(3)
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
t SA
t HA
t SD
t HD
DATA IN
(1)
t CD2
Dn + 2
Dn + 3
t CKLZ
t CD2
DATA OUT
Qn
(4)
Qn + 4
t OHZ
OE
READ
WRITE
READ
4830 drw 10
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0 , BE n , and ADS = V IL ; CE 1 , CNTEN , and CNTRST = V IH .
3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Pipelined Read with Address Counter Advance (1)
t CYC2
CLK
t CH2
t CL2
t SA
t HA
ADDRESS
ADS
CNTEN
An
t SAD t HAD
t CD2
t SAD t HAD
t SCN t HCN
DATA OUT
Qx - 1 (2)
Qx
Qn
Qn + 1
Qn + 2 (2)
Qn + 3
t DC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
4830 drw 11
NOTES:
1. CE 0 , OE , BE n = V IL ; CE 1 , R/ W , and CNTRST = V IH .
2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = V IL (advancing the address), i.e. ADS = V IH and CNTEN = V IH , then
the data output remains constant for subsequent clocks.
13
6.42
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