参数资料
型号: IDT70V38L15PFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/17页
文件大小: 0K
描述: IC SRAM 1.125MBIT 15NS 100TQFP
标准包装: 12
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 1.125M(64K x 18)
速度: 15ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
HIGH-SPEED 3.3V
64K x 18 DUAL-PORT
STATIC RAM
IDT70V38L
True Dual-Ported memory cells which allow simultaneous
Features
access of the same memory location
M/ S = V IH for BUSY output flag on Master,
M/ S = V IL for BUSY input on Slave
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V38L
Active: 440mW (typ.)
Standby: 660μW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V38 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
than one device
Functional Block Diagram
R/ W L
UB L
CE 0L
CE 1L
OE L
LB L
I/O 9-17L
I/O
I/O
R/ W R
UB R
CE 0R
CE 1R
OE R
LB R
I/O 9-17R
I/O 0-8L
BUSY L (1,2)
Control
Control
I/O 0-8R
(1,2)
BUSY R
.
A 15L
A 0L
Address
Decoder
64Kx18
MEMORY
ARRAY
70V38
Address
Decoder
A 15R
A 0R
16
16
SEM L
CE 0L
CE 1L
OE L
R/ W L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE 0R
CE 1R
OE R
R/ W R
SEM R
INT L
(2)
M/ S
(1)
INT R
(2)
NOTES:
1. BUSY is an input as a Slave (M/ S =V IL ) and an output when it is a Master (M/ S =V IH ).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
?2009 Integrated Device Technology, Inc.
4850 drw 01
JANUARY 2009
DSC-4850/4
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