参数资料
型号: IDT70V3579S6BF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/17页
文件大小: 0K
描述: IC SRAM 1.125MBIT 6NS 208FBGA
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 1.125M(32K x 36)
速度: 6ns
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-LFBGA
供应商设备封装: 208-CABGA(15x15)
包装: 带卷 (TR)
其它名称: 70V3579S6BF8
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation (2)
t CYC2
CLK
CE 0
t CH2
t CL2
t SC
t HC
t SC
t HC
(3)
CE 1
BE (0-3)
R/ W
t SB
t SW
t SA
t HB
t HW
t HA
t SB
(5)
t HB
ADDRESS
(4)
An
An + 1
An + 2
An + 3
(1 Latency)
t CD2
t DC
DATA OUT
t CKLZ
(1)
Qn
Qn + 1
t OHZ
t OLZ
Qn + 2
(5)
OE
(1)
t OE
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
4830 drw 06
2. ADS = V IL , CNTEN and CNTRST = V IH .
3. The output is disabled (High-Impedance state) by CE 0 = V IH , CE 1 = V IL , BE n = V IH following the next rising edge of the clock. Refer to Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BE n was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state).
Timing Waveform of a Multi-Device Pipelined Read (1,2)
t CYC2
CLK
t CH2
t CL2
t SA
t HA
ADDRESS (B1)
A 0
A 1
A 2
A 3
A 4
A 5
A 6
t SC
t HC
CE 0(B1)
t SC
t HC
DATA OUT(B1)
t CD2
Q 0
t CD2
Q 1
t CKHZ
t CD2
Q 3
t SA
t HA
t DC
t DC
t CKLZ
t CKHZ
ADDRESS (B2)
A 0
A 1
A 2
A 3
A 4
A 5
A 6
t SC
t HC
CE 0(B2)
t SC
t HC
DATA OUT(B2)
NOTES:
t CD2
t CKLZ
Q 2
t CKHZ
t CD2
t CKLZ
Q 4
4830 drw 07
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3579 for this waveform,
and are setup for depth expansion in this example. ADDRESS (B1) = ADDRESS (B2) in this situation.
2. BE n , OE , and ADS = V IL ; CE 1(B1) , CE 1(B2) , R/ W , CNTEN , and CNTRST = V IH .
11
6.42
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