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参数资料
| 型号： | IDT70V3579S6BF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/17页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 1.125MBIT 6NS 208FBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，同步 |
| 存储容量： | 1.125M（32K x 36） |
| 速度： | 6ns |
| 接口： | 并联 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 208-LFBGA |
| 供应商设备封装： | 208-CABGA（15x15） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70V3579S6BF8 |
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
Pin Names
Industrial and Commercial Temperature Ranges
Left Port
CE 0L , CE 1L
R/ W L
OE L
A 0L - A 14L
I/O 0L - I/O 35L
CLK L
ADS L
CNTEN L
CNTRST L
Right Port
CE 0R , CE 1R
R/ W R
OE R
A 0R - A 14R
I/O 0R - I/O 35R
CLK R
ADS R
CNTEN R
CNTRST R
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe Enable
Counter Enable
Counter Reset
BE 0L - BE 3L
V DDQL
OPT L
BE 0R - BE 3R
V DDQR
OPT R
V DD
V SS
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V) (1)
Option for selecting V DDQX (1,2)
Power (3.3V) (1)
Ground (0V)
NOTES:
1. V DD , OPT X , and V DDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT X selects the operating voltage levels on that port. If OPT X is set to VIH (3.3V),
then that port's I/Os and controls will operate at 3.3V levels and V DDQX must be
supplied at 3.3V. If OPT X is set to VIL (0V), then that port's I/Os and controls will
operate at 2.5V levels and V DDQX must be supplied at 2.5V. The OPT pins are
independent of one another—both ports can operate at 3.3V levels, both can
operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.
4830 tbl 01
Truth Table I—Read/Write and Enable Control (1,2,3,4)
Byte 3
Byte 2
Byte 1
Byte 0
OE
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
CE 0
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CE 1
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
BE 3
X
X
H
H
H
H
L
H
L
L
H
H
H
L
H
L
L
L
BE 2
X
X
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
L
BE 1
X
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
L
BE 0
X
X
H
L
H
H
H
L
H
L
L
H
H
H
L
H
L
L
R/ W
X
X
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
X
I/O 27-35
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D IN
High-Z
D IN
D IN
High-Z
High-Z
High-Z
D OUT
High-Z
D OUT
D OUT
High-Z
I/O 18-26
High-Z
High-Z
High-Z
High-Z
High-Z
D IN
High-Z
High-Z
D IN
D IN
High-Z
High-Z
D OUT
High-Z
High-Z
D OUT
D OUT
High-Z
I/O 9-17
High-Z
High-Z
High-Z
High-Z
D IN
High-Z
High-Z
D IN
High-Z
D IN
High-Z
D OUT
High-Z
High-Z
D OUT
High-Z
D OUT
High-Z
I/O 0-8
High-Z
High-Z
High-Z
D IN
High-Z
High-Z
High-Z
D IN
High-Z
D IN
D OUT
High-Z
High-Z
High-Z
D OUT
High-Z
D OUT
High-Z
MODE
Deselected –Power Down
Deselected –Power Down
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
Read Byte 0 Only
Read Byte 1 Only
Read Byte 2 Only
Read Byte 3 Only
Read Lower 2 Bytes Only
Read Upper 2 Bytes Only
Read All Bytes
Outputs Disabled
NOTES:
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. ADS , CNTEN , CNTRST = X .
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5
6.42
4830 tbl 02
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