参数资料
型号: IDT71V30S25TF
厂商: IDT, Integrated Device Technology Inc
文件页数: 9/14页
文件大小: 0K
描述: IC SRAM 8KBIT 25NS 64TQFP
标准包装: 40
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 8K (1K x 8)
速度: 25ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 托盘
其它名称: 71V30S25TF
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (6,7)
71V30X25
Com'l Only
71V30X35
Com'l & Ind
71V30X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=V IH )
t BAA
t BDA
t BAC
t BDC
t WH
t WDD
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY (5)
Write Pulse to Data Delay (1)
____
____
____
____
20
____
20
20
20
20
____
50
____
____
____
____
30
____
20
20
20
20
____
60
____
____
____
____
40
____
30
30
30
30
____
80
ns
ns
ns
ns
ns
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45
____
65
ns
t APS
t BDD
Arbitration Priority Set-up Time
BUSY Disable to Valid Data (3)
(2)
5
____
____
30
5
____
____
30
5
____
____
45
ns
ns
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read with BUSY".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that the Write Cycle is inhibited on Port “B” during contention on Port “A”.
5. To ensure that the Write Cycle is completed on Port “B” after contention on Port “A”.
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Write with Port-to-Port Read with BUSY (1,2,3,4)
t WC
3741 tbl 11
ADDR "A"
MATCH
t WP
R/ W "A"
t DW
t DH
DATA IN"A"
ADDR "B"
t APS (1)
VALID
MATCH
BUSY "B"
DATA OUT"B"
t BDA
t WDD
t BDD
VALID
t DDD
3741 drw 10
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CE L = CE R = V IL
3. OE = V IL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
9
6.42
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