参数资料
型号: IDT71V547S100PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/19页
文件大小: 0K
描述: IC SRAM 4MBIT 100NS 100TQFP
标准包装: 72
格式 - 存储器: RAM
存储器类型: SRAM - 同步 ZBT
存储容量: 4.5M(128K x 36)
速度: 100ns
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 71V547S100PF

tCYC
CLK
CEN
ADV / LD
R / W
tSADV
tSE
tSW
tSA
tHE
tHW
tHA
tCH
tHADV
tCL
ADDRESS
A1
A2
tSC
tHC
CE 1 , CE 2(2)
tSB
BW 1 - BW 4
B(A1)
tHB
B(A2)
B(A2+1)
B(A2+2)
B(A2+3)
B(A2)
OE
tSD
tHD
tS D
tHD
( CEN high, eliminates
current L-H clock edge)
(Burst Wraps around
to initial state)
DATA In
D(A1)
D(A2)
D(A2+1)
D(A2+2)
D(A2+3)
D(A2)
Write
Write
Burst Write
3822 drw 07
NOTES:
1. D (A 1 ) represents the first input to the external address A 1 . D (A 2 ) represents the first input to the external address A 2 ; D (A 2+1 ) represents the next input data in the burst sequence of the base
address A 2 , etc. where address bits A 0 and A 1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE 2 timing transitions are identical but inverted to the CE 1 and CE 2 signals. For example, when CE 1 and CE 2 are LOW on this waveform, CE 2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/ LD LOW.
4. R/ W is don't care when the SRAM is bursting (ADV/ LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/ W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals ( BW x) must be valid on all write and burst-write cycles. A write cycle is initiated when R/ W signal is sampled LOW. The byte write information
comes in one cycle before the actual data is presented to the SRAM.
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