参数资料
型号: IDT71V547S100PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 8/19页
文件大小: 0K
描述: IC SRAM 4MBIT 100NS 100TQFP
标准包装: 72
格式 - 存储器: RAM
存储器类型: SRAM - 同步 ZBT
存储容量: 4.5M(128K x 36)
速度: 100ns
接口: 并联
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 71V547S100PF
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT ? Feature, Burst Counter and Flow-Through Outputs
Read Operation (1)
Commercial and Industrial Temperature Ranges
Cycle
n
n+1
Address
A0
X
R/ W
H
X
ADV/ LD
L
X
CE (2)
L
X
CEN
L
X
BW x
X
X
OE
X
L
I/O
X
Q0
Comments
Address and Control meet setup
Co ntents of Address A0 Read Out
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE 2 timing transition is identical to CE 1 signal. CE 2 timing transition is identical but inverted to the CE 1 and CE 2 signals.
Burst Read Operation (1)
3822 tbl 12
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Address
A0
X
X
X
X
A1
X
A2
R/ W
H
X
X
X
X
H
X
H
ADV/ LD
L
H
H
H
H
L
H
L
CE (2)
L
X
X
X
X
L
X
L
CEN
L
L
L
L
L
L
L
L
BW x
X
X
X
X
X
X
X
X
OE
X
L
L
L
L
L
L
L
I/O
X
Q0
Q 0+1
Q 0+2
Q 0+3
Q0
Q1
Q 1+1
Comments
Address and Control meet setup
Address A0 Read Out, Inc. Count
Address A 0+1 Read Out, Inc. Count
Address A 0+2 Read Out, Inc. Count
Address A 0+3 Read Out, Load A1
Address A0 Read Out, Inc. Count
Address A1 Read Out, Inc. Count
Address A 1+1 Read Out, Load A2
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE 2 timing transition is identical to CE 1 signal. CE 2 timing transition is identical but inverted to the CE 1 and CE 2 signals.
Write Operation (1)
3822 tbl 13
Cycle
n
n+1
Address
A0
X
R/ W
L
X
ADV/ LD
L
X
CE (2)
L
X
CEN
L
L
BW x
L
X
OE
X
X
I/O
X
D0
Comments
Address and Control meet setup
Write to Address A0
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE 2 timing transition is identical to CE 1 signal. CE2 timing transition is identical but inverted to the CE 1 and CE 2 signals.
Burst Write Operation (1)
3822 tbl 14
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Address
A0
X
X
X
X
A1
X
A2
R/ W
L
X
X
X
X
L
X
L
ADV/ LD
L
H
H
H
H
L
H
L
CE (2)
L
X
X
X
X
L
X
L
CEN
L
L
L
L
L
L
L
L
BW x
L
L
L
L
L
L
L
L
OE
X
X
X
X
X
X
X
X
I/O
X
D0
D 0+1
D 0+2
D 0+3
D0
D1
D 1+1
Comments
Address and Control meet setup
Address A0 Write, Inc. Count
Address A 0+1 Write, Inc. Count
Address A 0+2 Write, Inc. Count
Address A 0+3 Write, Load A1
Address A0 Write, Inc. Count
Address A1 Write, Inc. Count
Address A 1+1 Write, Load A2
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE 2 timing transition is identical to CE 1 signal. CE 2 timing transition is identical but inverted to the CE 1 and CE 2 signals.
8
3822 tbl 15
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