参数资料
型号: IDT72V3622L10PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 27/29页
文件大小: 0K
描述: IC BIFIFO 256X36X2 10NS 120-TQFP
标准包装: 750
系列: 72V
功能: 异步,同步
存储容量: 18.4K(256 x 36 x 2)
数据速率: 100MHz
访问时间: 10ns
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 120-LQFP
供应商设备封装: 120-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 72V3622L10PF8
7
COMMERCIAL TEMPERATURERANGE
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3622/72V3632/72V3642 with
CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) +
Σ(CL x VCC2 X fo)
N
where:
N
=
number of outputs = 36
CL
=
output capacitance load
fo
=
switchingfrequencyofanoutput
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
010
20
30
40
50
60
70
0
25
50
75
100
125
150
VCC = 3.3V
fS
Clock Frequency
MHz
ICC(f)
Supply
Current
mA
fdata = 1/2 fS
TA = 25οC
CL = 0 pF
VCC = 3.0V
VCC = 3.6V
4660 drw 03a
175
200
80
90
100
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