- 您现在的位置：买卖IC网 > PDF目录10016 > IDT72V3634L15PF8 (IDT, Integrated Device Technology Inc)IC FIFO 512X36X2 15NS 128QFP PDF资料下载
参数资料
| 型号： | IDT72V3634L15PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/34页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 512X36X2 15NS 128QFP |
| 标准包装： | 1,000 |
| 系列： | 72V |
| 功能： | 异步，同步 |
| 存储容量： | 36.8K（512 x 36 x 2） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V3634L15PF8 |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
10
COMMERCIALTEMPERATURERANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SIGNAL DESCRIPTION
MASTER RESET (
MRS1, MRS2)
Afterpowerup,aMasterReset operationmustbeperformedbyproviding
a LOW pulse to
MRS1andMRS2simultaneously. Afterwards,eachofthetwo
FIFOmemoriesoftheIDT72V3624/72V3634/72V3644undergoesacomplete
reset by taking its associated Master Reset (
MRS1, MRS2) input LOW for at
least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH
transitions. TheMasterResetinputscanswitchasynchronouslytotheclocks.
A Master Reset initializes the associated write and read pointers to the first
location of the memory and forces the Full/Input Ready flag (
FFA/IRA, FFB/
IRB) LOW, the Empty/Output Ready flag (
EFA/ORA, EFB/ORB) LOW, the
Almost-Emptyflag(
AEA,AEB)LOWandforcestheAlmost-Fullflag(AFA,AFB)
HIGH. AMasterResetalsoforcestheassociatedMailboxFlag(
MBF1,MFB2)
of the parallel mailbox register HIGH. After a Master Reset, the FIFO's Full/
InputReadyflagissetHIGHaftertwowriteclockcycles. ThentheFIFOisready
to be written to.
A LOW-to-HIGH transition on the FIFO1 Master Reset (
MRS1) input
latches the values of the Big-Endian (BE) input for determining the order by
which bytes are transferred through Port B. It also latches the values of the
Flag Select (FS0, FS1) and Serial Programming Mode (
SPM) inputs for
choosingtheAlmost-FullandAlmost-Emptyoffsetprogrammingmethod.
ALOW-to-HIGHtransitionontheFIFO2MasterReset(
MRS2)clearsthe
Flag Offset Registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the
FIFO2 Master Reset (
MRS2) together with the FIFO1 Master Reset (MRS1)
input latches the value of the Big-Endian (BE) input for Port B and also latches
thevaluesoftheFlagSelect(FS0,FS1)andSerialProgrammingMode(
SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method. (For details see Table 1, Flag Programming, and the Programming
the Almost-Empty and Almost-Full Flags section). The relevant FIFO Master
Reset timing diagram can be found in Figure 3.
PARTIAL RESET (
PRS1, PRS2)
Each of the two FIFO memories of these devices undergoes a limited reset
bytakingitsassociatedPartialReset(
PRS1,PRS2)inputLOWforatleastfour
Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions.
The Partial Reset inputs can switch asynchronously to the clocks. A Partial
Reset initializes the internal read and write pointers and forces the Full/Input
Ready flag (
FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/
ORA,
EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the
Almost-Fullflag(
AFA,AFB)HIGH.APartialResetalsoforcestheMailboxFlag
(
MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,the
FIFO’s Full/Input Ready flag is set HIGH after two write clock cycles. Then
the FIFO is ready to be written to.
Whatever flag offsets, programming method (parallel or serial), and timing
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be inconvenient. See
Figure 4 for the Partial Reset timing diagram.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT)
— ENDIAN SELECTION
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction
is active, permitting a choice of Big or Little-Endian byte arrangement for data
writtentoorreadfromPortB.Thisselectiondeterminestheorderbywhichbytes
(or words) of data are transferred through this port. For the following
illustrations, assume that a byte (or word) bus size has been selected for Port
B. (Note that when Port B is configured for a long word size, the Big-Endian
function has no application and the BE input is a “don’t care”1.)
A HIGH on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputs go from LOW to HIGH will select a Big-Endian arrangement. When data
is moving in the direction from Port A to Port B, the most significant byte (word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written to
Port B first will be read from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port B last will be read from Port A as the least
significant byte (word) of the long word.
A LOW on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata
is moving in the direction from Port A to Port B, the least significant byte (word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written to
Port B first will be read from Port A as the least significant byte (word) of the long
word; the byte (word) written to Port B last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figure 2 for an illustration of
the BE function. See Figure 3 (Master Reset) for the Endian select timing
diagram.
— TIMING MODE SELECTION
After Master Reset, the FWFT select function is active, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (
MRS1,MRS2)inputisHIGH,
aHIGHontheBE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA
(for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (
EFA, EFB) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag function (
FFA,
FFB)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
In IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.
Once the Master Reset (
MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB)
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/
FWFTinputtochoose
the desired timing mode must remain static throughout FIFO operation. Refer
to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Four registers in the IDT72V3624/72V3634/72V3644 are used to hold the
offset values for the Almost-Empty and Almost-Full flags. The Port B Almost-
Emptyflag(
AEB)OffsetregisterislabeledX1andthePortAAlmost-Emptyflag
(
AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA) Offset
register is labeled Y1 and the Port B Almost-Full flag (
AFB) Offset register is
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.
相关PDF资料 |
PDF描述 |
|---|---|
| MS27499E14A15P | CONN RCPT 15POS BOX MNT W/PINS |
| LTC1345CNW#PBF | IC TXRX V.35 SINGLE SUPPLY 28DIP |
| LTC1345CNW | IC TXRX V.35 SINGLE SUPPLY 28DIP |
| IDT72821L15PFI | IC FIFO SYNC 1KX9 15NS 64QFP |
| MS27656T23A53P | CONN RCPT 53POS WALL MNT W/PINS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V3636L10PF | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3636L10PF8 | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3636L15PF | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3636L15PF8 | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3640L10PF | 功能描述:IC FIFO SS 1024X36 10NS 128-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
发布紧急采购，3分钟左右您将得到回复。