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参数资料
| 型号： | IDT72V3634L15PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 29/34页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 512X36X2 15NS 128QFP |
| 标准包装： | 1,000 |
| 系列： | 72V |
| 功能： | 异步，同步 |
| 存储容量： | 36.8K（512 x 36 x 2） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V3634L15PF8 |
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4
COMMERCIALTEMPERATURERANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bit bidirectional data port for side A.
AEA
Port A Almost-
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is
Empty Flag
less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB
Port B Almost-
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is
Empty Flag
less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA
Port A Almost-
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in
Full Flag
FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFB
Port B Almost-
O
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in
Full Flag
FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
B0-B35
Port A Data
I/O
36-bit bidirectional data port for side B.
BE/
FWFT
Big-Endian/
I
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this
First Word
case, depending on the bus size, the most significant byte or word on Port A is read from Port B first
Fall Through
(A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Little-Endian operation.
Select
In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or
written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on
FWFT selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has
been selected, the level on
FWFT must be static throughout device operation.
BM
Bus-Match
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A
Select
LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian
(Port B)
arrangement for Port B. The level of BM must be static throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous
or coincident to CLKB.
FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous
or coincident to CLKA.
FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH transition
of CLKB.
CSA
Port A Chip
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
Select
outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. The
Select
B0-B35 outputs are in the high-impedance state when
CSB is HIGH.
EFA/ORA
Port A Empty/
O
This is a dual function pin. In the IDT Standard mode, the
EFA function is selected. EFA indicates whether
Output Ready
or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the
Flag
presence of valid data on A0-A35 outputs, available for reading.
EFA/ORA is synchronized to the LOW-to-
HIGH transition of CLKA.
EFB/ORB
Port B Empty/
O
This is a dual function pin. In the IDT Standard mode, the
EFB function is selected. EFB indicates whether
Output Ready
or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the
Flag
presence of valid data on the B0-B35 outputs, available for reading.
EFB/ORBissynchronizedtotheLOW-to-
HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
FFA/IRA
Port A Full/
O
This is a dual function pin. In the IDT Standard mode, the
FFA function is selected. FFA indicates
Input Ready
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates
Flag
whether or not there is space available for writing to the FIFO1 memory.
FFA/IRA is synchronized to the
LOW-to-HIGH transition of CLKA.
FFB/IRB
Port B Full/
O
This is a dual function pin. In the IDT Standard mode, the
FFB function is selected. FFB indicates whether
Input Ready
or not the FIFO2 memory is full. In theFWFT mode, the IRB function is selected. IRB indicates whether or
Flag
not there is space available for writing to the FIFO2 memory.
FFB/IRB is synchronized to the LOW-to-HIGH
transition of CLKB.
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