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| 型号： | IDT72V3634L15PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/34页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 512X36X2 15NS 128QFP |
| 标准包装： | 1,000 |
| 系列： | 72V |
| 功能： | 异步，同步 |
| 存储容量： | 36.8K（512 x 36 x 2） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V3634L15PF8 |
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14
COMMERCIALTEMPERATURERANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array. For both FWFT and IDT Standard modes, each time
a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock have elapsed since
the next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 19, 20, 21, and 22).
ALMOST-EMPTY FLAGS (
AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
data from its array. The state machine that controls an Almost-Empty flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2.
The almost-empty state is defined by the contents of register X1 for
AEB and
register X2 for
AEA. These registers are loaded with preset values during a
FIFO reset, programmed from Port A, or programmed serially (see Almost-
Empty flag and Almost-Full flag offset programming section). An Almost-
Empty flag is LOW when its FIFO contains X or less words and is HIGH when
its FIFO contains (X+1) or more words. A data word present in the FIFO output
register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not elapsed since
the write that filled the memory to the (X+1) level. An Almost-Empty flag is set
HIGH by the second LOW-to-HIGH transition of its synchronizing clock after
the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition
of an Almost-Empty flag synchronizing clock begins the first synchronization
cycleifitoccursattimetSKEW2 orgreaterafterthewritethatfillstheFIFOto(X+1)
words. Otherwise, the subsequent synchronizing clock cycle may be the first
synchronization cycle. (See Figure 23 and 24).
ALMOST-FULL FLAGS (
AFA, AFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate
isdefinedbythecontentsofregisterY1for
AFAandregisterY2forAFB.These
registers are loaded with preset values during a FlFO reset, programmed from
Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag
offset programming section). An Almost-Full flag is LOW when the number of
words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y)
for the IDT72V3624, IDT72V3634, or IDT72V3644 respectively. An Almost-
Full flag is HIGH when the number of words in its FIFO is less than or equal
to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT72V3624,
IDT72V3634, or IDT72V3644 respectively. Note that a data word present in
the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock
are required after a FIFO read for its Almost-Full flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-
(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
not elapsed since the read that reduced the number of words in memory to
[256/512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-
to-HIGH transition of its synchronizing clock after the FIFO read that reduces
the number of words in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH
transition of an Almost-Full flag synchronizing clock begins the first synchro-
nization cycle if it occurs at time tSKEW2 or greater after the read that reduces
the number of words in memory to [256/512/1,024-(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figure 25 and 26).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between Port A and Port B without putting it in queue. The Mailbox
select (MBA, MBB) inputs choose between a mail register and a FIFO for a
port data transfer operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen
a Port A write is selected by
CSA, W/RA, and ENA with MBA HIGH. If the
selectedPortBbussizeisalso36bits,thentheusablewidthoftheMail1register
employs data lines A0-A35. If the selected Port B bus size is 18 bits, then the
usable width of the Mail1 Register employs data lines A0-A17. (In this case,
A18-A35 are don’t care inputs.) If the selected Port B bus size is 9 bits, then
the usable width of the Mail1 Register employs data lines A0-A8. (In this case,
A9-A35 are don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
Register when a Port B write is selected by
CSB, W/RB, and ENB with MBB
HIGH. If the selected Port B bus size is also 36 bits, then the usable width of
the Mail2 employs data lines B0-B35. If the selected Port B bus size is 18 bits,
then the usable width of the Mail2 Register employs data lines B0-B17. (In this
case, B18-B35 are don’t care inputs.) If the selected Port B bus size is 9 bits,
then the usable width of the Mail2 Register employs data lines B0-B8. (In this
case, B9-B35 are don’t care inputs.)
Writing data to a mail register sets its corresponding flag (
MBF1orMBF2)
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port Mailbox select input is HIGH.
The Mail1 Register Flag (
MBF1)issetHIGHbyaLOW-to-HIGHtransition
on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with MBB
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this
case, B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data
are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
The Mail2 Register Flag (
MBF2)issetHIGHbyaLOW-to-HIGHtransition
on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA
HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes only
whennewdataiswrittentotheregister.TheEndianselectfeaturehasnoeffect
onmailboxdata.FormailregisterandMailRegisterFlagtimingdiagrams,see
Figure 27 and 28.
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| IDT72V3636L10PF | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3636L10PF8 | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3636L15PF | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3636L15PF8 | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3640L10PF | 功能描述:IC FIFO SS 1024X36 10NS 128-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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