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| 型号： | IDT72V3654L15PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 23/37页 |
| 文件大小： | 0K |
| 描述： | IC BI FIFO 4096X36 15NS 128QFP |
| 标准包装： | 36 |
| 系列： | 72V |
| 功能： | 异步 |
| 存储容量： | 147K（4K x 36） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 72V3654L15PF |
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COMMERCIALTEMPERATURERANGE
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox
registers. The mailbox registers’ width matches the selected Port B bus width.
Each Mailbox register has a flag (
MBF1 and MBF2) to signal when new mail
has been stored.
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array, configures the FIFO for Big- or Little-Endian byte
arrangement and selects serial flag programming, parallel flag programming,
or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024. There
are two Master Reset pins,
MRS1 and MRS2.
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.
BothFIFO'shaveRetramsmitcapability,whenaRetransmitisperformed
on a respective FIFO only the read pointer is reset to the first memory location.
ARetransmitisperformedbyusingtheRetransmitMode,RTMpininconjunction
with the Retransmit pins
RT1 or RT2,for each respective FIFO. Note that the
two Retransmit pins
RT1 and RT2 are muxed with the Partial Reset pins.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
word written to an empty FIFO appears automatically on the outputs, no read
operation required (Nevertheless, accessing subsequent words does neces-
sitate a formal read request). The state of the BE/
FWFT pin during Master
Reset determines the mode in use.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstlong-
word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation is required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the BE/
FWFTpin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/
IRB). The
EF and FF functions are selected in the IDT Standard mode. EF
indicates whether or not the FIFO memory is empty.
FF shows whether the
memory is full or not. The IR and OR functions are selected in the First Word
FallThroughmode.IRindicateswhetherornottheFIFOhasavailablememory
locations. OR shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEA and AEB)
and a programmable Almost-Full flag (
AFA and AFB). AEA and AEB
indicate when a selected number of words remain in the FIFO memory.
AFA
and
AFB indicate when the FIFO contains more than a selected number of
words.
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the
port clock that writes data into its array.
EFA/ORA, EFB/ORB, AEA and
AEBaretwo-stagesynchronizedtotheportclockthatreadsdatafromitsarray.
Programmable offsets for
AEA, AEB, AFA and AFB are loaded in parallel
using Port A or in serial via the SD input. Five default offset settings are also
provided. The
AEA and AEB threshold can be set at 8, 16, 64, 256 or 1,024
locations from the empty boundary and the
AFA and AFB threshold can be
set at 8, 16, 64, 256 or 1,024 locations from the full boundary. All these choices
are made using the FS0, FS1 and FS2 inputs during Master Reset.
Interspersed Parity can also be selected during a Master Reset of the
FIFO.IfInterspersedParityisselectedthenduringparallelprogrammingofthe
flagoffsetvalues,thedevicewillignoredatalineA8.IfNon-InterspersedParity
is selected then data line A8 will become a valid bit.
Two or more devices may be used in parallel to create wider data paths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
TheIDT72V3654/72V3664/72V3674arecharacterizedforoperationfrom
0
°Cto70°C.Industrialtemperaturerange(-40°Cto+85°C)isavailable.They
are fabricated using IDT’s high speed, submicron CMOS technology.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V3654L15PF8 | 功能描述:IC BI FIFO 4096X36 15NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3656L10PF | 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3656L10PF8 | 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3656L10PFI | 制造商:Integrated Device Technology Inc 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP |
| IDT72V3656L10PFI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP |
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