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参数资料
| 型号： | IDT72V3654L15PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/37页 |
| 文件大小： | 0K |
| 描述： | IC BI FIFO 4096X36 15NS 128QFP |
| 标准包装： | 36 |
| 系列： | 72V |
| 功能： | 异步 |
| 存储容量： | 147K（4K x 36） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 72V3654L15PF |
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13
COMMERCIALTEMPERATURERANGE
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
offset values, the device will ignore data line A8. If Non-Interspersed Parity is
selectedthendatalineA8willbecomeavalidbit.IfInterspersedParityisselected
serial programming of the offset values is not permitted, only parallel program-
ming can be done.
— SERIAL LOAD
ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset
with FS2 LOW, FS0/SD LOW and FS1/
SEN HIGH during the LOW-to-HIGH
transition of
MRS1andMRS2.Afterthisresetiscomplete,theXandYregister
values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/
SEN input is LOW. There are 44-, 48-, or 52-
bitwritesneededtocompletetheprogrammingfortheIDT72V3654,IDT72V3664,
or IDT72V3674, respectively. The four registers are written in the order Y1,
TABLE 3 — PORT B ENABLE FUNCTION TABLE
the Port B Full/Input Ready flag (
FFB/IRB)issetHIGH,andbothFIFOsbegin
normal operation. Refer to Figure 5 for a timing diagram illustration of parallel
programming of the flag offset values.
INTERSPERSED PARITY
Interspersed Parity is selected during a Master Reset of the FIFO. Refer to
Table 1 for the set-up configuration of Interspersed Parity. The Interspersed
Parity function allows the user to select the location of the parity bits in the word
loadedintotheparallelport(A0-An)duringprogrammingoftheflagoffsetvalues.
If Interspersed Parity is selected then during parallel programming of the flag
CSA
W/
RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Function
H
X
High-Impedance
None
L
H
L
X
Input
None
LH
H
L
↑
Input
FIFO1 write
LH
H
↑
Input
Mail1 write
L
X
Output
None
LL
H
L
↑
Output
FIFO2 read
L
H
X
Output
None
LL
H
↑
Output
Mail2 read (set
MBF2 HIGH)
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Function
H
X
High-Impedance
None
L
X
Input
None
LL
H
L
↑
Input
FIFO2 write
LL
H
↑
Input
Mail2 write
L
H
L
X
Output
None
LH
H
L
↑
Output
FIFO1 read
L
H
L
H
X
Output
None
LH
H
↑
Output
Mail1 read (set
MBF1 HIGH)
X1,Y2,andfinally,X2. Thefirst-bitwritestoresthemostsignificantbitoftheY1
registerandthelast-bitwritestorestheleastsignificantbitoftheX2register.Each
register value can be programmed from 1 to 2,044 (IDT72V3654), 1 to 4,092
(IDT72V3664), or 1 to 8,188 (IDT72V3674).
When the option to program the offset registers serially is chosen, the Port
AFull/InputReady(
FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.
FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (
FFB/
IRB) flag also remains LOW throughout the serial programming process, until
allregisterbitsarewritten.
FFB/IRBissetHIGHbytheLOW-to-HIGHtransition
ofCLKBafterthelastbitisloadedtoallownormalFIFO2operation. SeeFigure 6
for Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset
Values (IDT Standard and FWFT Modes) timing diagram.
FIFO WRITE/READ OPERATION
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
(
CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh-
impedance state when either
CSA or W/RA is HIGH. The A0-A35 lines are
active outputs when both
CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and
FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when
CSA is LOW, W/RA is LOW,
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相关代理商/技术参数 |
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| IDT72V3654L15PF8 | 功能描述:IC BI FIFO 4096X36 15NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3656L10PF | 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3656L10PF8 | 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3656L10PFI | 制造商:Integrated Device Technology Inc 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP |
| IDT72V3656L10PFI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP |
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