- 您现在的位置：买卖IC网 > PDF目录9944 > IDT72V3672L10PF8 (IDT, Integrated Device Technology Inc)IC FIFO 16384X36 10NS 120QFP PDF资料下载
参数资料
| 型号： | IDT72V3672L10PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/29页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 16384X36 10NS 120QFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 异步，同步 |
| 存储容量： | 576K（16K x 36） |
| 数据速率： | 100MHz |
| 访问时间： | 10ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V3672L10PF8 |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
10
COMMERCIALTEMPERATURERANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
read request necessary. Subsequent words must be accessed by performing
a formal read operation.
Following Reset, the level applied to the
FWFTinputtochoosethedesired
timing mode must remain static throughout FIFO operation. Refer to Figure 2
(Reset) for a First Word Fall Through select timing diagram.
ALMOST-EMPTYFLAGANDALMOST-FULLFLAGOFFSETPROGRAM-
MING
Four registers in these devices are used to hold the offset values for the
Almost-EmptyandAlmost-Fullflags.TheportBAlmost-Emptyflag(
AEB)Offset
register is labeled X1 and the port A Almost-Empty flag (
AEA) Offset register
is labeled X2. The port A Almost-Full flag (
AFA) Offset register is labeled Y1
and the port B Almost-Full flag (
AFB) Offset register is labeled Y2. The index
ofeachregisternamecorrespondstoitsFIFOnumber.Theoffsetregisterscan
be loaded with preset values during the reset of a FIFO or they can be
programmed from port A (see Table 1).
FS0 and FS1 function the same way in both IDT Standard and FWFT
modes.
— PRESET VALUES
ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisters
withoneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselect
inputs must be HIGH during the LOW-to-HIGH transition of its reset input. For
example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be
HIGH when FlFO1 Reset (
RST1) returns HIGH. Flag offset registers
associatedwithFIFO2areloadedwithoneofthepresetvaluesinthesameway
with FIFO2 Reset (
RST2)toggledsimultaneouslywithFIFO1Reset(RST1).
For preset value loading timing diagram, see Figure 2.
— PARALLEL LOAD FROM PORT A
ToprogramtheX1,X2,Y1,andY2registersfromportA,bothFlFOsshould
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transitionoftheResetinputs.Itisimportanttonotethatonceparallelprogramming
hasbeenselectedduringaMasterResetbyholdingbothFS0&FS1LOW,these
inputs must remain LOW during all subsequent FIFO operation. They can only
be toggled HIGH when future Master Resets are performed and other
programming methods are desired.
After this reset is complete, the first four writes to FIFO1 do not store data
in the FIFO memory but load the offset registers in the order Y1, X1, Y2, X2.
SIGNAL DESCRIPTION
RESET
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding
a LOW pulse to
RST1 and RST2 simultaneously. Afterwards, the FIFO
memories of the IDT72V3652/72V3662/72V3672 are reset separately by
taking their Reset (
RST1, RST2) inputs LOW for at least four port-A Clock
(CLKA) and four port-B Clock (CLKB) LOW-to-HIGH transitions. The Reset
inputs can switch asynchronously to the clocks. A FIFO reset initializes the
internalreadandwritepointersandforcestheInputReadyflag(IRA,IRB)LOW,
the Output Ready flag (ORA, ORB) LOW, the Almost-Empty flag (
AEA,AEB)
LOW,andtheAlmost-Fullflag(
AFA,AFB)HIGH. ResettingaFIFOalsoforces
the Mailbox Flag (
MBF1, MBF2) of the parallel mailbox register HIGH. After
a FIFO is reset, its Input Ready flag is set HIGH after two clock cycles to begin
normal operation.
A LOW-to-HIGH transition on a FIFO Reset (
RST1,RST2)inputlatches
the value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and
Almost-Empty offset programming method. (For details see Table 1, Flag
Programming,andtheProgrammingtheAlmost-EmptyandAlmost-FullFlags
section). The relevant FIFO Reset timing diagram can be found in Figure 2.
FIRST WORD FALL THROUGH (
FWFT)
After Master Reset, the FWFT select function is active, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Reset (
RST1, RST2) input is HIGH, a
HIGH on the
FWFT input during the next LOW-to-HIGH transition of CLKA
(for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (
EFA, EFB) to indicate whether or not there
are any words present in the FIFO memory. It uses the Full Flag function (
FFA,
FFB) to indicate whether or not the FIFO memory has any free space for
writing. In IDT Standard mode, every word read from the FIFO, including the
first, must be requested using a formal read operation.
Once the Reset (
RST1, RST2) input is HIGH, a LOW on the FWFT input
during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for
FIFO2) will select FWFT mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at the data outputs
(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)toindicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to data outputs, no
NOTES:
1. X1 register holds the offset for
AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for
AEA; Y2 register holds the offset for AFB.
3. If parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
FS1
FS0
RST1
RST2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
HH
↑
X64
X
HH
X
↑
X64
HL
↑
X16
X
HL
X
↑
X16
LH
↑
X8
X
LH
X
↑
X8
LL
↑↑
Parallel programming via Port A(3)
TABLE 1 — FLAG PROGRAMMING
相关PDF资料 |
PDF描述 |
|---|---|
| MCZ33897TEFR2 | IC TXRX SGL WIRE CAN 14-SOIC |
| IDT72V283L7-5PF8 | IC FIFO 32768X18 7-5NS 80QFP |
| MS27466T15A35PA | CONN RCPT 37POS WALL MNT W/PINS |
| IDT72V283L10PFI8 | IC FIFO 32768X18 10NS 80QFP |
| V300B2M100B | CONVERTER MOD DC/DC 2V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V3672L10PQF | 功能描述:IC FIFO 16384X36 10NS 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3672L15PF | 功能描述:IC FIFO 16384X36 15NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3672L15PF8 | 功能描述:IC FIFO 16384X36 15NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3672L15PFI | 功能描述:IC FIFO 16384X36 15NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3672L15PQF | 功能描述:IC FIFO 16384X36 15NS 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
发布紧急采购，3分钟左右您将得到回复。