参数资料
型号: IDT79RC32T336-150BCG
厂商: IDT, Integrated Device Technology Inc
文件页数: 26/44页
文件大小: 0K
描述: IC MPU 32BIT CORE 150MHZ 256-BGA
标准包装: 90
系列: Interprise™
处理器类型: MIPS32 32-位
速度: 150MHz
电压: 2.5V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 79RC32T336-150BCG
32 of 44
October 4, 2005
RC32336
The IEEE 1149.1 specification requires that the JTAG and EJTAG TAP controllers be reset at power-up whether or not the interfaces are used for
a boundary scan or a probe. Reset can occur through a pull-down resistor on JTAG_TRST_N if the probe is not connected. However, on-chip pull-up
resistors are implemented on the RC32336 due to an IEEE 1149.1 requirement. Having on-chip pull-up and external pull-down resistors for the
JTAG_TRST_N signal requires special care in the design to ensure that a valid logical level is provided to JTAG_TRST_N, such as using a small
external pull-down resistor to ensure this level overrides the on-chip pull-up. An alternative is to use an active power-up reset circuit for
JTAG_TRST_N, which drives JTAG_TRST_N low only at power-up and then holds JTAG_TRST_N high afterwards with a pull-up resistor.
Figure 21 shows the electrical connection of the EJTAG probe target system connector.
Figure 21 Target System Electrical EJTAG Connection
Using the EJTAG Probe
In Figure 21, the pull-up resistors for JTAG_TDO and RST*, the pull-down resistor for JTAG_TRST_N, and the series resistor for JTAG_TDO must
be adjusted to the specific design. However, the recommended pull-up/down resistor is 1.0 k
because a low value reduces crosstalk on the cable to
the connector, allowing higher JTAG_TCK frequencies. A typical value for the series resistor is 33
. Recommended resistor values have ± 5% toler-
ance.
If a probe is used, the pull-up resistor on JTAG_TDO must ensure that the JTAG_TDO level is high when no probe is connected and the
JTAG_TDO output is tri-stated. This requirement allows reliable connection of the probe if it is hooked-up when the power is already on (hot plug). The
pull-up resistor value of around 47 k
should be sufficient. Optional diodes to protect against overshoot and undershoot voltage can be added on the
signals of the chip with EJTAG.
If a probe is used, the RST* signal must have a pull-up resistor because it is controlled by an open-collector (OC) driver in the probe, and thus is
actively pulled low only. The pull-up resistor is responsible for the high value when not driven by the probe of 25pF. The input on the target system
reset circuit must be able to accept the rise time when the pull-up resistor charges the capacitance to a high logical level. Vcc I/O must connect to a
voltage reference that drops rapidly to below 0.5V when the target system loses power, even with a capacitive load of 25pF. The probe can thus detect
the lost power condition.
For additional information on EJTAG, refer to Chapter 23 of the RC32336 User Reference Manual.
GND
1
GND
TRST*
TDI
TDO
TMS
TCK
RST*
JTAG_TRST_N
JTAG_TDI
JTAG_TDO
EJTAG_TMS
JTAG_TCK
GND
VDD
GND
Pu
ll-
up
Pul
l-dow
n
Series-res.
COLDRSTN
Target System
Reset Circuit
Pu
ll-
up
Other reset
sources
RC32336
no connect
or RSTN
VSENSE
2
GND
no connect
GND
Pu
ll-
up
Vcc I/O
Voltage reference
23 24
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