参数资料
型号: IDT79RC32T336-150BCG
厂商: IDT, Integrated Device Technology Inc
文件页数: 42/44页
文件大小: 0K
描述: IC MPU 32BIT CORE 150MHZ 256-BGA
标准包装: 90
系列: Interprise™
处理器类型: MIPS32 32-位
速度: 150MHz
电压: 2.5V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 79RC32T336-150BCG
7 of 44
October 4, 2005
RC32336
PCIREQN[1:0]
I/O
PCI Bus Request.
In PCI host mode with internal arbiter:
These signals are inputs whose assertion indicates to the internal RC32336 arbiter that an agent
desires ownership of the PCI bus.
In PCI host mode with external arbiter:
PCIREQN[0]: asserted by the RC32336 to request ownership of the PCI bus.
PCIREQN[1]: unused and driven high.
In PCI satellite mode:
PCIREQN[0]: this signal is asserted by the RC32336 to request ownership of the PCI bus.
PCIREQN[1]: function changes to PCIIDSEL and is used as a chip select during configuration
read and write transactions.
PCIRSTN
I/O
PCI Reset. In host mode, this signal is asserted by the RC32336 to generate a PCI reset. In sat-
ellite mode, assertion of this signal initiates a warm reset.
PCISERRN
I/O
PCI System Error. This signal is driven by an agent to indicate an address parity error, data par-
ity error during a special cycle command, or any other system error. Requires an external pull-up.
PCISTOPN
I/O
PCI Stop. Driven by the bus target to terminate the current bus transaction. For example, to indi-
cate a retry.
PCITRDYN
I/O
PCI Target Ready. Driven by the bus target to indicate that the current data can complete.
Ethernet Interface
MII0CL
I
Ethernet 0 MII Collision Detected. This signal is asserted by the ethernet PHY when a collision
is detected.
MII0CRS
I
Ethernet 0 MII Carrier Sense. This signal is asserted by the ethernet PHY when either the trans-
mit or receive medium is not idle.
MII0RXCLK
I
Ethernet 0 MII Receive Clock. This clock is a continuous clock that provides a timing reference
for the reception of data.
MII0RXD[3:0]
I
Ethernet 0 MII Receive Data. This nibble wide data bus contains the data received by the ether-
net PHY.
MII0RXDV
I
Ethernet 0 MII Receive Data Valid. The assertion of this signal indicates that valid receive data
is in the MII receive data bus.
MII0RXER
I
Ethernet 0 MII Receive Error. The assertion of this signal indicates that an error was detected
somewhere in the ethernet frame currently being sent in the MII receive data bus.
MII0TXCLK
I
Ethernet 0 MII Transmit Clock. This clock is a continuous clock that provides a timing reference
for the transfer of transmit data.
MII0TXD[3:0]
O
Ethernet 0 MII Transmit Data. This nibble wide data bus contains the data to be transmitted.
MII0TXENP
O
Ethernet 0 MII Transmit Enable. The assertion of this signal indicates that data is present on the
MII for transmission.
MII0TXER
O
Ethernet 0 MII Transmit Coding Error. When this signal is asserted together with MIITXENP,
the ethernet PHY will transmit symbols which are not valid data or delimiters.
MII1CL
I
Ethernet 1 MII Collision Detected. This signal is asserted by the ethernet PHY when a collision
is detected.
MII1CRS
I
Ethernet 1 MII Carrier Sense. This signal is asserted by the ethernet PHY when either the trans-
mit or receive medium is not idle.
MII1RXCLK
I
Ethernet 1 MII Receive Clock. This clock is a continuous clock that provides a timing reference
for the reception of data.
Signal
Type
Name/Description
Table 1 Pin Description (Part 4 of 6)
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