参数资料
型号: IDT79RC32T336-150BCG
厂商: IDT, Integrated Device Technology Inc
文件页数: 43/44页
文件大小: 0K
描述: IC MPU 32BIT CORE 150MHZ 256-BGA
标准包装: 90
系列: Interprise™
处理器类型: MIPS32 32-位
速度: 150MHz
电压: 2.5V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 79RC32T336-150BCG
8 of 44
October 4, 2005
RC32336
MII1RXD[3:0]
I
Ethernet 1 MII Receive Data. This nibble wide data bus contains the data received by the ether-
net PHY.
MII1RXDV
I
Ethernet 1 MII Receive Data Valid. The assertion of this signal indicates that valid receive data
is in the MII receive data bus.
MII1RXER
I
Ethernet 1 MII Receive Error. The assertion of this signal indicates that an error was detected
somewhere in the ethernet frame currently being sent in the MII receive data bus.
MII1TXCLK
I
Ethernet 1 MII Transmit Clock. This clock is a continuous clock that provides a timing reference
for the transfer of transmit data.
MII1TXD[3:0]
O
Ethernet 1 MII Transmit Data. This nibble wide data bus contains the data to be transmitted.
MII1TXENP
O
Ethernet 1 MII Transmit Enable. The assertion of this signal indicates that data is present on the
MII for transmission.
MII1TXER
O
Ethernet 1 MII Transmit Coding Error. When this signal is asserted together with MIITXENP,
the ethernet PHY will transmit symbols which are not valid data or delimiters.
MIIMDC
O
MII Management Data Clock. This signal is used as a timing reference for transmission of data
on the management interface.
MIIMDIO
I/O
MII Management Data. This bidirectional signal is used to transfer data between the station man-
agement entity and the ethernet PHY.
EJTAG / JTAG
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or
JTAG Controller. When using the EJTAG debug interface, this pin should be left disconnected
(since there is an internal pull-up) or driven high.
EJTAG_TMS
I
EJTAG Mode. The value on this signal controls the test mode select of the EJTAG Controller.
When using the JTAG boundary scan, this pin should be left disconnected (since there is an inter-
nal pull-up) or driven high.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary scan logic, JTAG TAP
Controller, and the EJTAG Debug TAP Controller. An external pull-up on the board is recom-
mended to meet the JTAG specification in cases where the tester can access this signal. How-
ever, for systems running in functional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high.
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the bound-
ary scan logic, JTAG Controller, or the EJTAG Controller. JTAG_TCK is independent of the sys-
tem and the processor clock with a nominal 50% duty cycle.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary scan logic, JTAG Con-
troller, or the EJTAG Controller. When no data is being shifted out, this signal is tri-stated.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic, JTAG Controller, or the
EJTAG Controller.
Signal
Type
Name/Description
Table 1 Pin Description (Part 5 of 6)
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