参数资料
型号: IDT79RC32V334-133BB8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
封装: 17 X 17 MM, PLASTIC, BGA-256
文件页数: 2/30页
文件大小: 652K
代理商: IDT79RC32V334-133BB8
10 of 30
November 1, 2001
79RC32334
JTAG Interface Signals
jtag_tck
Input
JTAG Test Clock Requires an external pull-down.
An input test clock used to shift into or out of the Boundary-Scan register cells. jtag_tck is independent of
the system and the processor clock with nominal 50% duty cycle.
jtag_tdi,
ejtag_dint_n
Input
JTAG Test Data In Requires an external pull-up.
On the rising edge of jtag_tck, serial input data are shifted into either the Instruction or Data register, depend-
ing on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the debug
unit from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG). This pin is
also used as the ejtag_dint_n signal in the EJTAG mode.
jtag_tdo,
ejtag_tpc
Output
High
JTAG Test Data Out
The jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. When
no data is shifted out, the jtag_tdo is tri-stated. During Real Time Mode, this signal provides a non-sequen-
tial program counter at the processor clock or at a division of processor clock. This pin is also used as the
ejtag_tpc signal in the EJTAG mode.
jtag_tms
Input
JTAG Test Mode Select Requires an external pull-up.
The logic signal received at the jtag_tms input is decoded by the TAP controller to control test operation.
jtag_tms is sampled on the rising edge of the jtag_tck.
jtag_trst_n
Input
JTAG Test Reset
The jtag_trst_n pin is an active-low signal for asynchronous reset of the debug unit, independent of the pro-
cessor logic. An external pull-up on the board is recommended to meet the JTAG specification in cases
where the tester can not access this signal, however, specific systems ordinarily should either
1) drive low this signal
2) use an external pulldown on the board
3) clock jtag_tclk
ejtag_dclk
Output
EJTAG Test Clock
Processor Clock. During Real Time Mode, this signal is used to capture address and data from the ejtag_tpc
signal at the processor clock speed or any division of the internal pipeline.
ejtag_pcst[2:0]
I/O
Low
EJTAG PC Trace Status Information
111 (STL) Pipe line Stall
110 (JMP) Branch/Jump forms with PC output
101 (BRT) Branch/Jump forms with no PC output
100 (EXP) Exception generated with an exception vector code output
011 (SEQ) Sequential performance
010 (TST) Trace is outputted at pipeline stall time
001 (TSQ) Trace trigger output at performance time
000 (DBM) Run Debug Mode
Alternate function: modebit[2:0].
ejtag_debugboot
Input
EJTAG DebugBoot Requires an external pull-down.
The ejtag_debugboot input is used during reset and forces the CPU core to take a debug exception at the
end of the reset sequence instead of a reset exception. This enables the CPU to boot from the ICE probe
without having the external memory working. This input signal is level sensitive and is not latched internally.
This signal will also set the JtagBrk bit in the JTAG_Control_Register[12].
ejtag_tms
Input
EJTAG Test Mode Select Requires an external pull-up.
The ejtag_tms is sampled on the rising edge of jtag_tck.
Name
Type
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 6 of 7)
相关PDF资料
PDF描述
IDT79RC32V334-150BB9 32-BIT, 150 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-133BBI9 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V364-100DAGI 32-BIT, 100 MHz, RISC PROCESSOR, PQFP144
IDT79RC64T574250DZG 64-BIT, 250 MHz, RISC PROCESSOR, PQFP128
IDT79RC64T575-200DPG 64-BIT, 200 MHz, RISC PROCESSOR, PQFP208
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