参数资料
型号: IDT79RC32V334-133BB8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
封装: 17 X 17 MM, PLASTIC, BGA-256
文件页数: 29/30页
文件大小: 652K
代理商: IDT79RC32V334-133BB8
8 of 30
November 1, 2001
79RC32334
sdram_bemask_n[3:0] Output
High
SDRAM Byte Enable Mask Negated Bus (DQM)
SDRAM mode: Provides byte enables for each byte lane of all DRAM banks.
SODIMM mode: Provides lower select byte enables [3:0].
sdram_245_oe_n
Output
Low
SDRAM FCT245 Output Enable Negated Recommend an external pull-up.
SDRAM mode: Controls output enable to optional FCT245 transceiver bank by asserting during both reads
and writes to any DRAM bank.
sdram_245_dt_r_n
Output
High
SDRAM FCT245 Direction Transmit/Receive Recommend am external pull-up.
Uses cpu_dt_r_n. See CPU Core Specific Signals below.
On-Chip Peripherals
dma_ready_n[1:0] /
dma_done_n[1:0]
I/O
Low
DMA Ready Negated Bus Requires an external pull-up.
Ready mode: Input pin for each general purpose DMA channel that can initiate the next datum in the current
DMA descriptor frame.
Done mode: Input pin for each general purpose DMA channel that can terminate the current DMA descriptor
frame.
dma_ready_n[0] 1st Alternate function PIO[1]; 2nd Alternate function: dma_done_n[0].
dma_ready_n[1] 1st Alternate function PIO[0]; 2nd Alternate function: dma_done_n[1].
pio[15:0]
I/O
Low
Programmable Input/Output
General purpose pins that can each be configured as a general purpose input or general purpose output.
These pins are multiplexed with other pin functions:
uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0], pci_gnt_n[1], spi_mosi, spi_sck, spi_ss, spi_miso,
uart_rx[0], uart_tx[0], uart_rx[1], uart_tx[1], timer_tc_n[0], dma_ready_n[0], dma_ready_n[1]. Note that spi-
mosi, spi_miso, spi_sck, and spi_ss default to outputs at reset time. The others default to inputs.
timer_tc_n[0] /
timer_gate_n[0]
I/O
Low
Timer Terminal Count Overflow Negated
Terminal count mode (timer_tc_n): Output indicating that the timer has reached its count compare value and
has overflowed back to 0.
Gate mode (timer_gate_n): input indicating that the timer may count one tick on the next clock edge.
1st Alternate function: PIO[2].
2nd Alternate function: timer_gate_n[0].
uart_rx[1:0]
I/O
Low
UART Receive Data Bus
UART mode: Each UART channel receives data on their respective input pin.
uart_rx[0] Alternate function: PIO[6].
uart_rx[1] Alternate function: PIO[4].
uart_tx[1:0]
I/O
Low
UART Transmit Data Bus Recommend an external pull-up.
UART mode: Each UART channel sends data on their respective output pin. Note that these pins default to
inputs at reset time and must be programmed via the PIO interface before being used as UART outputs.
uart_tx[0] Alternate function: PIO[5].
uart_tx[1] Alternate function: PIO[3].
uart_cts_n[0]
uart_dsr_n[0]
uart_dtr_n[0]
uart_rts_n[0]
I/O
Low
UART Transmit Data Bus
UART mode: Data bus modem control signal pins for UART channel 0.
uart_cts_n[0] Alternate function: PIO[15].
uart_dsr_n[0] Alternate function: PIO[14].
uart_dtr_n[0] Alternate function: PIO[13].
uart_rts_n[0] Alternate function: PIO[12].
Name
Type
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 4 of 7)
相关PDF资料
PDF描述
IDT79RC32V334-150BB9 32-BIT, 150 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-133BBI9 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V364-100DAGI 32-BIT, 100 MHz, RISC PROCESSOR, PQFP144
IDT79RC64T574250DZG 64-BIT, 250 MHz, RISC PROCESSOR, PQFP128
IDT79RC64T575-200DPG 64-BIT, 200 MHz, RISC PROCESSOR, PQFP208
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