参数资料
型号: IDT79RC32V334-133BB8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
封装: 17 X 17 MM, PLASTIC, BGA-256
文件页数: 30/30页
文件大小: 652K
代理商: IDT79RC32V334-133BB8
9 of 30
November 1, 2001
79RC32334
spi_mosi
I/O
Low
SPI Data Output
Serial mode: Output pin from RC32334 as an Input to a Serial Chip for the Serial data input stream.
In PCI satellite mode, acts as an Output pin from RC32334 that connects as an Input to a Serial Chip for the
Serial data input stream for loading PCI Configuration Registers in the RC32334 Reset Initialization Vector
PCI boot mode.
Defaults to the output direction at reset time.
1st Alternate function: PIO[10].
2nd Alternate function: pci_eeprom_mdo.
spi_miso
I/O
Low
SPI Data Input
Serial mode: Input pin to RC32334 from the Output of a Serial Chip for the Serial data output stream.
In PCI satellite mode, acts as an Input pin from RC32334 that connects as an output to a Serial Chip for the
Serial data output stream for loading PCI Configuration Registers in the RC32334 Reset Initialization Vector
PCI boot mode.
Defaults to input direction at reset time.
1st Alternate function: PIO[7].
2nd Alternate function: pci_eeprom_mdi.
spi_sck
I/O
Low
SPI Clock
Serial mode: Output pin for Serial Clock.
In PCI satellite mode, acts as an Output pin for Serial Clock for loading PCI Configuration Registers in the
RC323334 Reset Initialization Vector PCI boot mode.
Defaults to the output direction at reset time.
1st Alternate function: PIO[9].
2nd Alternate function: pci_eeprom_sk.
spi_ss_n
I/O
Low
SPI Chip Select
Output pin selecting the serial protocol device as opposed to the PCI satellite mode EEPROM device.
Alternate function: PIO[8]. Defaults to the output direction at reset time.
CPU Core Specific Signals
cpu_nmi_n
Input
CPU Non-Maskable Interrupt Requires an external pullup.
This interrupt input is active low to the CPU.
cpu_masterclk
Input
CPU Master System Clock
Provides the basic system clock.
cpu_int_n[5:4], [2:0]
Input
CPU Interrupt Requires an external pullup.
These interrupt inputs are active low to the CPU.
cpu_coldreset_n
Input
CPU Cold Reset
This active-low signal is asserted to the RC32334 after
Vcc becomes valid on the initial power-up. The
Reset initialization vectors for the RC32334 are latched by cold reset.
cpu_dt_r_n
Output
CPU Direction Transmit/Receive
This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during
read operations.
1st Alternate function: mem_245_dt_r_n.
2nd Alternate function: sdram_245_dt_r_n.
Name
Type
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 5 of 7)
相关PDF资料
PDF描述
IDT79RC32V334-150BB9 32-BIT, 150 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-133BBI9 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V364-100DAGI 32-BIT, 100 MHz, RISC PROCESSOR, PQFP144
IDT79RC64T574250DZG 64-BIT, 250 MHz, RISC PROCESSOR, PQFP128
IDT79RC64T575-200DPG 64-BIT, 200 MHz, RISC PROCESSOR, PQFP208
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