参数资料
型号: IDT82V2088BB
厂商: IDT, Integrated Device Technology Inc
文件页数: 32/78页
文件大小: 0K
描述: IC LIU T1/J1/E1 8CH 208-BGA
标准包装: 10
类型: 线路接口装置(LIU)
规程: E1
电源电压: 3.13 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 208-BGA
供应商设备封装: 208-PBGA(17x17)
包装: 托盘
其它名称: 82V2088BB
38
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-24 Per Channel Register List and Map
Address (Hex)
Register R/W
Map
CH1-CH8
b7
b6
b5
b4
b3
b2
b1
b0
Jitter Attenuation Control Register
01,21,41,61,81,A1,C1,E1 JACF
R/W
-
JA_LIMIT
JACF1
JACF0
JADP1
JADP0
JABW
Transmit Path Control Registers
02,22,42,62,82,A2,C2,E2 TCF0
R/W
-
T_OFF
TD_INV
TCLK_SEL
T_MD1
T_MD0
03,23,43,63,83,A3,C3,E3 TCF1
R/W
-
DFM_OFF
THZ
PULS3
PULS2
PULS1
PULS0
04,24,44,64,84,A4,C4,E4 TCF2
R/W
-
SCAL5
SCAL4
SCAL3
SCAL2
SCAL1
SCAL0
05,25,45,65,85,A5,C5,E5 TCF3
R/W
DONE
RW
UI1
UI0
SAMP3
SAMP2
SAMP1
SAMP0
06,26,46,66,86,A6,C6,E6 TCF4
R/W
-
WDAT6
WDAT5
WDAT4
WDAT3
WDAT2
WDAT1
WDAT0
Receive Path Control Registers
07,27,47,67,87,A7,C7,E7 RCF0
R/W
-
R_OFF
RD_INV
RCLK_SEL
R_MD1
R_MD0
08,28,48,68,88,A8,C8,E8 RCF1
R/W
-
EQ_ON
-
LOS4
LOS3
LOS2
LOS1
LOS0
09,29,49,69,89,A9,C9,E9 RCF2
R/W
-
SLICE1
SLICE0
UPDW1
UPDW0
MG1
MG0
Network Diagnostics Control Registers
0A,2A,4A,6A,8A,AA,CA,EA MAINT0 R/W
-
PATT1
PATT0
PATT_CLK
PRBS_INV
LAC
AISE
ATAO
0B,2B,4B,6B,8B,AB,CB,EB MAINT1
-
ARLP
RLP
ALP
DLP
0C,2C,4C,6C,8C,AC,CC,EC MAINT2 R/W
-
TIBLB_L1
TIBLB_L0
RIBLBA_L1
RIBLBA_L0 RIBLBD_L1 RIBLBD_L0
0D,2D,4D,6D,8D,AD,CD,ED MAINT3 R/W
TIBLB7
TIBLB6
TIBLB5
TIBLB4
TIBLB3
TIBLB2
TIBLB1
TIBLB0
0E,2E,4E,6E,8E,AE,CE,EE MAINT4 R/W
RIBLBA7
RIBLBA6
RIBLBA5
RIBLBA4
RIBLBA3
RIBLBA2
RIBLBA1
RIBLBA0
0F,2F,4F,6F,8F,AF,CF,EF
MAINT5 R/W
RIBLBD7
RIBLBD6
RIBLBD5
RIBLBD4
RIBLBD3
RIBLBD2
RIBLBD1
RIBLBD0
10,30,50,70,90,B0,D0,F0
MAINT6 R/W
-
BPV_INS
ERR_INS
EXZ_DEF
ERR_SEL1
ERR_SEL0
CNT_MD
CNT_TRF
Interrupt Control Registers
11,31,51,71,91,B1,D1,F1
INTM0
R/W
EQ_IM
IBLBA_IM
IBLBD_IM
PRBS_IM
TCLK_IM
DF_IM
AIS_IM
LOS_IM
12,32,52,72,92,B2,D2,F2
INTM1
R/W DAC_OV_IM
JAOV_IM
JAUD_IM
ERR_IM
EXZ_IM
CV_IM
TIMER_IM
CNT_IM
13,33,53,73,93,B3,D3,F3
INTES
R/W
EQ_IES
IBLBA_IES
IBLBD_IES PRBS_IES
TCLK_IES
DF_IES
AIS_IES
LOS_IES
Line Status Registers
14,34,54,74,94,B4,D4,F4
STAT0
R
EQ_S
IBLBA_S
IBLBD_S
PRBS_S
TCLK_LOS
DF_S
AIS_S
LOS_S
15,35,55,75,95,B5,D5,F5
STAT1
R
-
RLP_S
LATT4
LATT3
LATT2
LATT1
LATT0
Interrupt Status Registers
16,36,56,76,96,B6,D6,F6
INTS0
R
EQ_IS
IBLBA_IS
IBLBD_IS
PRBS_IS TCLK_LOS_IS
DF_IS
AIS_IS
LOS_IS
17,37,57,77,97,B7,D7,F7
INTS1
R
DAC_OV_IS
JAOV_IS
JAUD_IS
ERR_IS
EXZ_IS
CV_IS
TMOV_IS CNT_OV_IS
Counter Registers
18,38,58,78,98,B8,D8,F8
CNT0
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
19,39,59,79,99,B9,D9,F9
CNT1
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Transmit and Receive Termination Registers
1A,3A,5A,7A,9A,BA,DA,FA TERM
R/W
-
T_TERM2
T_TERM1
T_TERM0
R_TERM2
R_TERM1
R_TERM0
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