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| 型号： | IDT82V3255 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | WAN PLL |
| 中文描述： | 广域网锁相环 |
| 文件页数： | 34/127页 |
| 文件大小： | 868K |
| 代理商： | IDT82V3255 |
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IDT82V3255
WAN PLL
Functional Description
34
June 19, 2006
3.11
T0 / T4 DPLL OUTPUT
The DPLL output is locked to the selected input clock. According to
the phase-compared result of the feedback and the selected input clock,
and the DPLL output frequency offset, the PFD output is limited and the
DPLL output is frequency offset limited.
3.11.1
PFD OUTPUT LIMIT
The PFD output is limited to be within ±1 UI or within the coarse
phase limit (refer to
Chapter 3.7.1.2 Coarse Phase Loss
), as determined
by the MULTI_PH_APP bit.
3.11.2
FREQUENCY OFFSET LIMIT
The DPLL output is limited to be within the DPLL hard limit (refer to
Chapter 3.7.1.4 Hard Limit Exceeding
).
For T0 DPLL, the integral path value can be frozen when the DPLL
hard limit is reached. This function, enabled by the T0_LIMT bit, will min-
imize the subsequent overshoot when T0 DPLL is pulling in.
3.11.3
PBO (T0 ONLY)
The PBO function is only supported by the T0 path.
When a PBO event is triggered, the phase offset of the selected input
clock with respect to the T0 DPLL output is measured. The device then
automatically accounts for the measured phase offset and compensates
an appropriate phase offset into the DPLL output so that the phase tran-
sients on the T0 DPLL output are minimized.
A PBO event is triggered if any one of the following conditions
occurs:
T0 selected input clock switches (the PBO_EN bit is ‘1’);
T0 DPLL exits from Holdover mode or Free-Run mode (the
PBO_EN bit is ‘1’);
Phase-time changes on the T0 selected input clock are greater
than a programmable limit over an interval of less than 0.1 sec-
onds (the PH_MON_PBO_EN bit is ‘1’).
For the first two conditions, the phase transients on the T0 DPLL out-
put are minimized to be no more than 0.61 ns with PBO. The PBO can
also be frozen at the current phase offset by setting the PBO_FREZ bit.
When the PBO is frozen, the device will ignore any further PBO events
triggered by the above two conditions, and maintain the current phase
offset. When the PBO is disabled, there may be a phase shift on the T0
DPLL output and the T0 DPLL output tracks back to 0 degree phase off-
set with respect to the T0 selected input clock.
The last condition is specially for stratum 2 and 3E clocks. The PBO
requirement specified in the Telcordia GR-1244-CORE is: ‘Input phase-
time changes of 3.5 μs or greater over an interval of less than 0.1 sec-
onds or less shall be built-out by stratum 2 and 3E clocks to reduce the
resulting clock phase-time change to less than 50 ns. Phase-time
changes of 1.0 μs or less over an interval of 0.1 seconds shall not be
built-out.’ Based on this requirement, phase-time changes of more than
1.0 μs but less than 3.5 μs that occur over an interval of less than 0.1
seconds may or may not be built-out.
An integrated Phase Transient Monitor can be enabled by the
PH_MON_EN bit to monitor the phase-time changes on the T0 selected
input clock. When the phase-time changes are greater than a limit over
an interval of less than 0.1 seconds, a PBO event is triggered and the
phase transients on the DPLL output are absorbed. The limit is pro-
grammed by the PH_TR_MON_LIMT[3:0] bits, and can be calculated as
follows:
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156
The phase offset induced by PBO will never result in a coarse or fine
phase loss.
3.11.4
PHASE OFFSET SELECTION (T0 ONLY)
The phase offset of the T0 selected input clock with respect to the T0
DPLL output can be adjusted. The PH_OFFSET_EN bit determines
whether the input-to-output phase offset is enabled. If enabled, the
input-to-output phase offset can be adjusted by setting the
PH_OFFSET[9:0] bits.
The input-to-output phase offset can be calculated as follows:
Phase Offset (ns) = PH_OFFSET[9:0] X 0.61
3.11.5
FOUR PATHS OF T0 / T4 DPLL OUTPUTS
The T0 DPLL output and the T4 DPLL output are phase aligned with
the T0 selected input clock and the T4 selected input clock respectively
every 125 μs period. Each DPLL has four output paths.
3.11.5.1
T0 Path
The four paths for T0 DPLL output are as follows:
77.76 MHz path - outputs a 77.76 MHz clock;
16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by
the IN_SONET_SDH bit;
GSM/OBSAI/16E1/16T1 path - outputs a GSM, OBSAI, 16E1 or
16T1 clock, as selected by the T0_GSM_OBSAI_16E1_16T1_
SEL[1:0
]
bits;
12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock,
as selected by the T0_12E1_24T1_E3_T3_SEL[1:0] bits.
T0 selected input clock is compared with a T0 DPLL output for DPLL
locking. The output can only be derived from the 77.76 MHz path or the
16E1/16T1 path. The output path is automatically selected and the out-
put is automatically divided to get the same frequency as the T0
selected input clock.
The T0 DPLL 77.76 MHz output or an 8 kHz signal derived from it
can be provided for the T4 DPLL input clock selection (refer to
Chapter 3.6 T0 / T4 DPLL Input Clock Selection
).
T0 DPLL outputs are provided for T0/T4 APLL or device output pro-
cess.
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| IDT82V3255DK | WAN PLL |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3255_08 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DKG | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3255DKG8 | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3255EDGBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
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