- 您现在的位置：买卖IC网 > PDF目录377488 > IDT82V3280 (Integrated Device Technology, Inc.) WAN PLL PDF资料下载
参数资料
| 型号： | IDT82V3280 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | WAN PLL |
| 中文描述： | 广域网锁相环 |
| 文件页数： | 8/167页 |
| 文件大小： | 1039K |
| 代理商： | IDT82V3280 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页
List of Figures
8
June 19, 2006
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 21
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 23
Figure 5. External Fast Selection ................................................................................................................................................................................ 25
Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 26
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 32
Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 33
Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 42
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 42
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 43
Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 43
Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 44
Figure 14. IDT82V3280 Power Decoupling Scheme ................................................................................................................................................... 46
Figure 15. Typical Application ...................................................................................................................................................................................... 47
Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 49
Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 50
Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 51
Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 52
Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 53
Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 54
Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 55
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 56
Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 56
Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 57
Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 58
Figure 27. 64 kHz + 8 kHz Signal Structure .............................................................................................................................................................. 151
Figure 28. 64 kHz + 8 kHz + 0.4 kHz Signal Structure .............................................................................................................................................. 151
Figure 29. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level ................................................................................................................ 151
Figure 30. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level ............................................................................................................. 151
Figure 31. AMI Input / Output Port Line Termination (Recommended) ..................................................................................................................... 152
Figure 32. Recommended PECL Input Port Line Termination .................................................................................................................................. 154
Figure 33. Recommended PECL Output Port Line Termination ................................................................................................................................ 154
Figure 34. Recommended LVDS Input Port Line Termination .................................................................................................................................. 156
Figure 35. Recommended LVDS Output Port Line Termination ................................................................................................................................ 156
Figure 36. Output Wander Generation ...................................................................................................................................................................... 160
Figure 37. Input / Output Clock Timing ...................................................................................................................................................................... 161
List of Figures
相关PDF资料 |
PDF描述 |
|---|---|
| IDT82V3280DQ | WAN PLL |
| IDT82V3280DQG | WAN PLL |
| IDT82V3280PF | WAN PLL |
| IDT82V3280PFG | WAN PLL |
| IDT82V3288 | WAN PLL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3280_08 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280APFG | 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3280APFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP |
| IDT82V3280DQ | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280DQG | 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
发布紧急采购，3分钟左右您将得到回复。