参数资料
型号: IPR-SDI
厂商: Altera
文件页数: 45/140页
文件大小: 0K
描述: IP VIDEO INTERFACE - SDI RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: 视频系统用串行数字接口
许可证: 续用许可证
Chapter 3: Functional Description
3–15
Block Description
Receiver Clocks
The transceiver requires a receiver reference clock, rx_serial_refclk . This clock
trains the receiver PLL in the transceiver.
For HD-SDI operation, the clock must be nominally 1/20 th of the serial data rate. The
clock do not have to operate at the data rate, because it is only used for the training of
the receiver PLL.
For SD-SDI operation, the clock must be nominally 1/4 th of the serial data rate (for
example, 67.5 MHz). The clock do not have to be frequency-locked to the data.
For dual standard operation, the receiver reference clock must be 67.5 MHz, which
allows the transceiver to sample the data for SD-SDI at the correct frequency. For
HD-SDI, the receiver PLL trains with the 67.5-MHz reference, and then tracks to the
actual incoming data rate.
All receiver interfaces can share a common receiver reference clock.
Table 3–6 lists the frequencies of the receiver clock, rx_serial_refclk , for Stratix GX
devices.
Table 3–6. Receiver Clock Frequency—Stratix GX Devices
SD-SDI
Video Standard (1)
Clock Frequency (MHz)
67.5
HD-SDI (including dual link)
Dual standard
Notes to Table 3–6 :
(1) Stratix GX devices do not support 3G-SDI and triple standard modes.
(2) The rx_serial_refclk signal must be externally multiplexed.
74.175/74.25
67.5
February 2013
Altera Corporation
Serial Digital Interface (SDI) MegaCore Function
User Guide
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