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参数资料
型号： IPR-SDI
厂商： Altera
文件页数： 47/140页
文件大小： 0K
描述： IP VIDEO INTERFACE - SDI RENEW
标准包装： 1
系列： *
类型： MegaCore
功能： 视频系统用串行数字接口
许可证： 续用许可证
Chapter 3: Functional Description
3–17
Block Description
For HD-SDI, the FIFO buffer realigns the parallel video input to the transceiver
tx_coreclk clock. It is written on every tx_pclk clock, and read on every tx_coreclk .
For SD-SDI, the FIFO buffer also provides the rate conversion required by the
transmitter oversampling logic. It is written on every other tx_pclk , using the SD-SDI
data width conversion logic. It is read on every fifth tx_coreclk . This operation
ensures that the transmitter oversampling logic is provided with a word of parallel
video data on every fifth clock.
HD-SDI Two-Times Oversampling
This mode performs two-times oversampling and runs the transceiver at double rate,
which gives better output jitter performance. This mode requires a higher rate
reference clock, refer to Table 3–5 on page 3–14 .
SD-SDI Transmitter Oversampling
SD-SDI requires a 270-Mbps serial data rate, which is achieved by transmitting a
1,350 Mbps signal with each bit repeated five times. This process ensures that the
transceiver runs at a supported frequency.
Receiver Transceiver Interface
Altera provides a transceiver interface, which interfaces the transceiver to the SDI
function. The transceiver interface implements the following functions:
■
■
SD-SDI Receiver Oversampling
Transceiver Controller
1
When using the two-times oversampling transmitters in Stratix GX devices, you
cannot have HD-SDI receivers in the same quad. The quad requires the same
frequency reference clocks for both the receivers and transmitters within a quad.
HD-SDI receivers and two-times oversampling transmitters have different frequency
reference clocks (refer to Table 3–5 on page 3–14 and Table 3–6 on page 3–15).
SD-SDI Receiver Oversampling
The Stratix GX transceiver does not support CDR for data rates less than 500 Mbps.
The receiver uses fixed frequency oversampling for the reception of 270-Mbps
SD-SDI. The serial data is sampled by the transceiver at 1,350 Mbps and the original
270-Mbps data is extracted by the SD-SDI receiver oversampling logic.
Figure 3–10 shows an example of the receiver data timing.
Figure 3–10. Receiver Data Timing
rx_clk (67.5MHz)
rxdata
rx_data_valid_out
DATA
February 2013
Altera Corporation
Serial Digital Interface (SDI) MegaCore Function
User Guide
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相关代理商/技术参数
参数描述
IPR-SDI-II 功能描述:开发软件 SDI II Video MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-SDRAM/DDR 功能描述:开发软件 DDR SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-SDRAM/DDR2 功能描述:开发软件 DDR2 SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-SDRAM/DDR3 功能描述:开发软件 DDR3 SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-SDRAM/HPDDR 功能描述:开发软件 DDR SDRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
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