参数资料
型号: IR3513ZMTRPBF
厂商: International Rectifier
文件页数: 12/36页
文件大小: 0K
描述: IC CTRL XPHASE3 POL 32-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 3mA
电源电压: 8 V ~ 16 V
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 带卷 (TR)
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3513ZMTRPBF
IR3513
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the XPhase TM architecture is shown in Figure 3. Feed-forward voltage mode control with
trailing edge modulation is used. A voltage-type error amplifier with high-gain (110dB) and wide-bandwidth is used
for the control loop. It is not unity gain stable. The power-stage input voltage is sensed by the IR3513, and optional
phase ICs, to provide feed-forward control. The PWM ramp slope will change with the input voltage and
automatically compensate for changes in the input voltage. The input voltage can change due to variations in the
silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current.
VOSNS+
VOSNS-
IR3513 CONTROL IC
VCC
CLOCK GENERATOR
VIN
CLK Q
D
PWM
VCCH
IC BIAS
LATCH
S
GATEH
CBST
REMOTE SENSE +
PWM
COMPARATOR
-
RESET
DOMINANT
R
SW
VCCL
COUT
VOUT
ENABLE
+
GATEL
GND
REMOTE SENSE
AMPLIFIER
VID6
RAMP
DISCHARGE
BODY
BRAKING
COMPARATOR
PGND
REMOTE SENSE -
CLAMP
SHARE ADJUST
ERROR AMPLIFIER
CURRENT
ERROR
VREF
+
-
3K
-
VID6
VID6
+
VID6
SENSE
AMPLIFIER
CSIN+
CCS
RCS
AMPLIFIER
VID6 +
+
CSIN-
VO
FB
PHSOUT
CLKIN
PHASE IC
VCC
CLK Q
D
PWM
VCCH
RFB1
CFB
RFB
RCOMP
CCOMP
CCOMP1
PHSIN
PWM
COMPARATOR
LATCH
S
RESET
DOMINANT
GATEH
SW
CBST
EAIN
-
+
ENABLE
VID6
RAMP
DISCHARGE
R
BODY
BRAKING
COMPARATOR
VCCL
GATEL
PGND
CLAMP
SHARE ADJUST
ERROR AMPLIFIER
CURRENT
ISHARE
3K
-
VID6
VID6
+
SENSE
AMPLIFIER
CSIN+
Control Bus to
additional Phases
DACIN
VID6
VID6 +
+
CSIN-
CCS
RCS
Power Bus to
additional Phases
Figure 3 - PWM Block Diagram
Frequency and Phase Timing Control
The oscillator system clock frequency is programmable from 500 kHz to 9 MHZ by an external resistor. The IR3513
system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is
controlled by the daisy chain loop, where the IR3513 phase clock output (PHSOUT) is connected to the phase clock
input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase
IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to complete the loop . During
power up, the IR3513 sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at
PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 4 shows the phase
timing for a four-phase converter. For single-phase operation, PHSOUT (pin 26) and PHSIN (pin 27) must be
shorted together to prevent an Open Control Loop fault from occurring.
Page 12
May 11, 2008
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