参数资料
型号: IR3513ZMTRPBF
厂商: International Rectifier
文件页数: 2/36页
文件大小: 0K
描述: IC CTRL XPHASE3 POL 32-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 3mA
电源电压: 8 V ~ 16 V
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 带卷 (TR)
ORDERING INFORMATION
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3513ZMTRPBF
IR3513
Device
IR3513MTRPBF
* IR3513MPBF
?
Samples only
PIN DESCRIPTION
Package
32 Lead MLPQ (5 x 5 mm body)
32 Lead MLPQ(5 x 5 mm body)
Order Quantity
3000 per reel
100 piece strips
PIN#
1
2
3
4
5
6, 24
7
8
9
10
11
12
13
14, 28
15
16
17
18
19
20
21
22
PIN SYMBOL
GATEH
BOOST
VCCP
GATEL
PGND
LGND
CSIN+
CSIN-
ENABLE
PG
MARGIN
VOSEN-
VOSEN+
VCCL
VOUT
OVSNS
FB
EAOUT
IIN
OCSET
VREF
SS/DEL
PIN DESCRIPTION
High-side driver output and input to GATEL non-overlap comparator.
Supply for high-side driver. An internal bootstrap synchronous PFET is connected
between this pin and the VCCP pin.
Supply for low-side driver. An internal bootstrap synchronous PFET is connected
from this pin to the BOOST pin.
Low-side driver output and input to GATEH non-overlap comparator.
Return for low side driver and reference for GATEH non-overlap comparator.
Local Ground for internal circuitry and the IC substrate connection.
Non-Inverting input to the current sense amplifier and input to debug comparator.
Inverting input to the current sense amplifier and input to synchronous rectification
disable comparator.
Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float
this pin as the logic state will be undefined.
Open drain output that drives low during startup and under any external fault
condition. Connect external pull-up.
Tri-state input with internal pull-up to 1.425 V. Low/High voltage shifts the Error
Amplifier reference voltage Up/Down 5%. V(MARGIN) should not be biased to a
voltage greater than V(VCCL).
Inverting remote sense amplifier input. Connect to ground at the load.
Non-inverting remote sense amplifier input. Connect to output at the load.
Output of the voltage regulator, power input for clock oscillator circuitry and other
internal circuitry. Connect a decoupling capacitor to LGND.
Remote sense amplifier output.
Over voltage sense input during normal operation.
Inverting input to the Error Amplifier.
Output of the Error Amplifier.
Average current input signal from active and inactive phase IC(s). This pin is also
used to communicate an over voltage condition to the phase IC(s).
An external resistor tied to VREF along with a fixed internal current source
programs the constant output current limit and hiccup over-current thresholds.
Over-current protection can be disabled by programming the threshold higher than
the possible signal on the IIN pin, but no greater than 5V (do not float this pin).
Reference voltage for the Error Amplifier. An external RC network to LGND
programs the margin slew rate and compensates the internal buffer amp.
An external capacitor to LGND programs converter startup and over current
protection delay timing. It is also used to compensate the constant output current
loop during soft start.
Page 2
May 11, 2008
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相关代理商/技术参数
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