参数资料
型号: IR3521MTRPBF
厂商: International Rectifier
文件页数: 28/45页
文件大小: 0K
描述: IC CTRL XPHASE3 SVID 32-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 10mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 带卷 (TR)
IR3521
DESIGN PROCEDURES - IR3521 AND IR3508 CHIPSET
IR3521 EXTERNAL COMPONENTS
All the output components are selected using one output but suitable for both unless otherwise specified.
Oscillator Resistor R R osc
The IR3521 generates square wave pulses to synchronize the phase ICs. The switching frequency of the each
phase converter equals the PHSOUT frequency, which is set by the external resistor R ROSC (use Figure 2 to
determine the R ROSC value). The CLKOUT frequency equals the switching frequency multiplied by the phase
number.
Soft Start Capacitor C SS/DEL
The Soft Start capacitor C SS/DEL programs four different time parameters: soft start delay time, soft start time,
PGOOD delay time and over-current fault latch delay time after PGOOD.
SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 11. Once the ENABLE
pin rises above 1.65V, there is a soft-start delay time TD1 during which SS/DEL pin is charged from zero to 1.4V.
Once SS/DEL reaches 1.4V the error amplifier output is released to allow the soft start. The soft start time, TD2,
represents the time during which converter voltage rises from zero to pre-PWROK VID voltage and the SS/DEL pin
voltage rises from 1.4V to pre-PWROK VID voltage plus 1.4V. PGOOD delay time TD3 is the time period from VR
reaching the pre-PWROK VID voltage to the PGOOD signal assertion.
Calculate C SS/DEL based on the required soft start time TD2.
C SS / DEL
?
TD 2 * I CHG
V pre ? PWROK
?
TD 2 * 50 * 10 ? 6
V pre ? PWROK
(1)
The soft start delay time TD1 and PGOOD delay time TD3 are determined by equation (2) and (3) respectively.
TD 1 ?
C SS / DEL * 1 . 4
I CHG
?
C SS / DEL * 1 .4
50 * 10 ? 6
(2)
TD 3 ?
C SS / DEL * (3 . 92 ? V pre ? PWROK ? 1 . 4 )
I CHG
?
C SS / DEL * (3 . 92 ? V pre ? PWROK ? 1 . 4 )
50 * 10 ? 6
(3)
Once C SS/DEL is chosen, use equation (4) to calculate the maximum over-current fault latch delay time t OCDEL.
t OCDEL ?
C SS / DEL * 0. 12
I DISCHG
?
C SS / DEL * 0.12
47 * 10 ? 6
(4)
VDAC Slew Rate Programming Capacitor C VDAC and Resistor R VDAC
The slew rate of VDAC down-slope SR DOWN can be programmed by the external capacitor C VDAC as defined in (5),
where I SINK is the VDAC buffer sink current. The resistor R VDAC is used to compensate VDAC circuit and is
determined by (6). The up and down slow are equal due to symmetrical sink and source capabilities of the VDAC
buffer.
Page 28
V3.03
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