参数资料
型号: IR3521MTRPBF
厂商: International Rectifier
文件页数: 3/45页
文件大小: 0K
描述: IC CTRL XPHASE3 SVID 32-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 10mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 带卷 (TR)
IR3521
PIN DESCRIPTION
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PIN SYMBOL
SVD
PWROK
ENABLE
IIN2
SS/DEL2
VDAC2
OCSET2
EAOUT2
FB2
VOUT2
VOSEN2+
VOSEN2-
VOSEN1-
VOSEN1+
VOUT1
FB1
EAOUT1
OCSET1
VDAC1
PIN DESCRIPTION
SVD (Serial VID Data) is a bidirectional signal that is an input and open drain output
for both master (AMD processor) and slave (IR3521), requires an external bias
voltage and should not be floated
System wide Power Good signal and input to the IR3521. When asserted, the
IR3521 output voltage is programmed through the SVID interface protocol.
Connecting this pin to VCCL enables VFIX mode.
Enable input. A logic low applied to this pin puts the IC into fault mode. A logic high
on the pin enables the converter and causes the SVC and SVD input states to be
decoded and stored, determining the 2-bit Boot VID. Do not float this pin as the logic
state will be undefined.
Output 2 average current input from the output 2 phase IC(s). This pin is also used
to communicate over voltage condition to the output 2 phase ICs.
Programs output 2 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
Output 2 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
Programs the output 2 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC2 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC2 to program the threshold higher than the possible
signal into the IIN2 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
Output of the output 2 error amplifier.
Inverting input to the Output 2 error amplifier.
Output 2 remote sense amplifier output.
Output 2 remote sense amplifier input. Connect to output at the load.
Output 2 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to ground at the load.
Output 1 remote sense amplifier input. Connect to output at the load.
Output 1 remote sense amplifier output.
Inverting input to the output 1 error amplifier. Converter output voltage can be
increased from the VDAC1 voltage with an external resistor connected between
VOUT1 and this pin (there is an internal current sink at this pin).
Output of the output 1 error amplifier.
Programs the output 1 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC1 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC1 to program the threshold higher than the possible
signal into the IIN1 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
Output 1 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
Page 3
V3.03
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