参数资料
型号: IR3523MTRPBF
厂商: International Rectifier
文件页数: 11/37页
文件大小: 0K
描述: IC XPHASE3 CTLR VR11.1 40-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 10mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-MLPQ
供应商设备封装: 40-MLPQ(6x6)
包装: 带卷 (TR)
IR3523
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the xPHASE3
TM
architecture is shown in Figure 5. Feed-forward voltage mode control
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The
PWM ramp slope will change with the input voltage automatically compensating for changes in the input voltage.
The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace
voltage drop related to changes in load current.
IR3523 CONTROL IC
GATE DRIVE
VOLTAGE
VIN
PHSOUT
PHASE IC
VCC
CLOCK GENERATOR
CLKOUT
CLKIN
CLK Q
D
PWM
VCCH
PHSOUT
PHSIN
PHSIN
PWM
COMPARATOR
LATCH
S
RESET
DOMINANT
GATEH
SW
CBST
VOSNS1+
VOUT1
EAIN
-
+
R
VCCL
COUT
GND
REMOTE SENSE
AMPLIFIER
+
-
VOUT1
ENABLE
+
VID6
-
RAMP
DISCHARGE
BODY
BRAKING
COMPARATOR
GATEL
PGND
VOSNS1-
VDAC1
LGND
CLAMP
SHARE ADJUST
+
-
ERROR
+
-
ERROR AMPLIFIER
AMPLIFIER
VDAC
+
-
EAOUT1
RCP1
CCP12
RFB12
RFB11
ISHARE
3K
+
-
-
VID6
VID6
+
VID6
VID6 +
CURRENT
SENSE
AMPLIFIER
+
-
CSIN+
CCS RCS
CCP11
+
CSIN-
FB1
CFB1
DACIN
IFB1
IROSC
VDRP1 AMP
+
VDRP1
CDRP1
RDRP1
PHSOUT
PHASE IC
VCC
-
CLKIN
CLK Q
VCCH
Output 1 Only
IIN1
PHSIN
D
PWM
LATCH
S
GATEH
CBST
PWM
COMPARATOR
RESET
DOMINANT
SW
EAIN
-
+
ENABLE
+
VID6
-
RAMP
DISCHARGE
CLAMP
R
BODY
BRAKING
COMPARATOR
+
-
VCCL
GATEL
PGND
SHARE ADJUST
ERROR AMPLIFIER
+
CURRENT
ISHARE
3K
-
-
VID6
VID6
+
SENSE
AMPLIFIER
CSIN+
VID6
VID6 +
+
+
-
CSIN-
CCS RCS
DACIN
Figure 5 - PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 500kHz to 9MHZ
by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs.
The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output
(PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is
connected to PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of
the control IC. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and
detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop.
Figure 6 shows the phase timing for a four phase converter.
Page 11 of 37
June 20, 2008
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