参数资料
型号: IR3523MTRPBF
厂商: International Rectifier
文件页数: 9/37页
文件大小: 0K
描述: IC XPHASE3 CTLR VR11.1 40-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 10mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-MLPQ
供应商设备封装: 40-MLPQ(6x6)
包装: 带卷 (TR)
IR3523
IR3523 block diagram
ENABLE2
-
+
250nS
BLANKING
1.65V
1.0V
ENABLE
COMPARATOR
250nS
BLANKING
ENABLE
-
+
ENABLE1
PG2
UV2
COMPARATOR
1.65V
1.0V
VCCLDRV
SSCLF2
DLY OUT2
OVLATCH
UV1
DLY OUT1
400k
PG1
400k
VCCLDRV
VCCLFB
1.2V
VCCL REGULATOR
AMPLIFIER
0.94
0.86
OV1_2
S Q
SET
DOMINANT
R
VCCL UVLO
OC2 AFTER VRRDY
OC2 Bf VRRDY
SS/DEL CLEARED
FAULT LATCH2
S Q
SET
SS/DEL CLEARED
FAULT LATCH1
Q S
SET
DOMINANT
R
VCCL UVLO
OC1 AFTER VRRDY
OC1 Bf VRRDY
UV CLEARED
FAULT LATCH1
INTERNAL
CIRCUIT DIS
BIAS
OV
OPEN DAISY
VCCL
DOMINANT
Q
S
OPEN SENSE1
OV
VCCL UVL
COMPARATOR
UV CLEARED
FAULT LATCH2
R
SET
DOMINANT
R
OPEN CONTROL1
OPEN DAISY
DIS
DELAY
OPEN SENSE2
OPEN CONTROL2
S Q
SET
DOMINANT
OC DELAY
PHSOUT
POWER-UP
OK LATCH
80mV
COMPARATOR 120mV
DIS DIS
TBS
80mV
120mV
R
DELAY
COMPARATOR
DLY OUT2
POWER-UP
OK LATCH
S Q
PHSOUT
IROSC
OC
DIS DELAY
COUTER
DIS
COUTER DIS
reset
IROSC
Q S
RESET
DOMINANT
Q R
DLY OUT1
DISCHARGE
COMPARATOR
-
3.9V
SSCLF1
DISCHARGE
COMPARATOR
RESET
DOMINANT
R Q
reset
+
0.2V
ICHG
50uA
IDCHG
SS/DEL2
SSCLF2
ICHG
50uA
OV2
VCCL
0.2V
DIS
-
+
IDCHG
4.5uA
DIS
FLT2
DCHG2
IDCHG2
47uA
IDCHG1
47uA
DIS
DCHG1
FLT1
4.5uA
PHSOUT
OC LIMIT
COMPARATOR
DIS
DIS
8 Pulse
Delay
OV1
VCCL
-
+
VDRP
AMPLIFIER
SS/DEL1
VDRP1
IIN1
DIS
DIS
8 Pulse
Delay
PHSOUT
OC LIMIT
IROSC
IOCSET
OPEN CONTROL
LOOP COMPARATOR
-
0.3V
VCCL
OCSET1
IIN2
OCSET2
0.3V
OPEN CONTROL
COMPARATOR
OV1_2
FLT1
1.4V
+
DISABLE1
VCCL
-
LOOP COMPARATOR
IROSC
SOFT
START
VDAC1
EAOUT1
+
DISABLE2
FLT2
1.4V
IOCSET
DLY OUT2
DLY OUT1
CLAMP
ERROR
AMPLIFIER
FB1
EAOUT2
FB2
UV2
ERROR
AMPLIFIER
VOUT2 UV
COMPARATOR
VDAC2
275mV
315mV
OVER VOLTAGE
COMPARATOR
-
SOFT
START
CLAMP
125mV
OV2
OV2
OV1
PG2
PG1
OV1
1.2V
125mV
-
+
VDAC1
OVER
VOLTAGE
COMPARATOR
IROSC
275mV
315mV
IFB
VOUT1 UV
COMPARATOR
UV1
OV2
+
VDAC2
1.8V
DYNAMIC VID2 DOWN
DETECT COMPARATOR
50mV
DYNAMIC VID1 DOWN
DETECT COMPARATOR
DETECTION PULSE1
OV1
VOUT2
VOSEN2+
VOSEN2-
IVOSEN2-
25k
25k
25k
IVOSEN2+
REMOTE SENSE
60mV
50mV
60mV
REMOTE SENSE
AMPLIFIER
25k
25k
25k
IVOSEN1+
IVOSEN1-
VOUT1
VOSEN1+
VOSEN1-
IVOSEN-
AMPLIFIER
25k
25k
VIDSEL
IVOSEN-
VCCL
VCCL
VIDSEL
200mV
-
VCCL
DETECTION PULSE1
VCCL
DETECTION PULSE2
-
200mV
+
0.4V
LINE DETECT
VCCL*0.9
-
+
+
4 OPEN SENSE
VCCL RESET
COMPARATORS
OPEN SENSE LINE2
4 OPEN SENSE
LINE DETECT
COMPARATORS
OPEN SENSE LINE1
VCCL RESET
-
+
VCCL*0.9
0.4V
-
-
+
+
ISOURCE
VDAC2
ISOURCE
IROSC
IROSC
ISINK
VDAC1
ISINK
VDAC BUFFER
VDAC BUFFER
AMPLIFIER
DIGITAL TO
ANALOG
CONVERTERS
AMPLIFIER
VDAC
VCCL UVLO FAULT
VID2_2
VID2_1
VID2_0
VID2
VID3
175k
VID0
1.0V
INTERNAL
VID3
VID2
VID1
VIDSEL
DYNAMIC DOWN VID2
VID0
OPEN DAISY
CHAIN
PHSIN
IROSC
CURRENT
SOURCE
GENERATOR
ROSC BUFFER
AMPLIFIER
0.6V
LGND
VDAC
DELAY COMPARATOR
VID1_4
VID1_3
VID1_2
VID2
VID3
175k
1.0V
VID0
VID INPUT
COMPARATORS
INTERNAL
VID3
VID2
VID1
VIDSEL
DYNAMIC DOWN VID1
VBOOT FAULT LATCH 1
Q S
(1.1V)
SET
DOMINANT
SAMPLE DELAY
R
CLKOUT PHSOUT
CLKOUT PHSIN PHSOUT
VID1 SAMPLE AND
SS/DEL1
OV
VCCL - 1.2V
ROSC
Page 9 of 37
(1 of 3 SHOWN)
3.0V
Figure 3 – IR3523 BLOCK DIAGRAM
June 20, 2008
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